Patents by Inventor Donald P. Monroe

Donald P. Monroe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6518622
    Abstract: The present invention provides a VRG structure formed on a semiconductor wafer substrate. The VRG structure has a first source/drain region located in a semiconductor wafer substrate, and a conductive layer located adjacent the source/drain region, a second source/drain region and a conductive channel that extends from the first source/drain region to the second source/drain region. The conductive layer provides an electrical connection to the first source/drain region. The conductive layer may have a low sheet resistance that may be less than about 50 &OHgr;/square or less than about 20 &OHgr;/square, to the first source/drain region.
    Type: Grant
    Filed: March 20, 2000
    Date of Patent: February 11, 2003
    Assignee: Agere Systems Inc.
    Inventors: Hongzong Chew, Yih-Feng Chyan, John M. Hergenrother, Yi Ma, Donald P. Monroe
  • Patent number: 5620496
    Abstract: The present invention is predicated upon the discovery by applicants of a relationship describing thermal decay of radiation-induced index changes and a mechanism which permits stabilization by accelerated aging. Specifically, the induced index change decays in proportion to 1/(1+At.sup..alpha.) where A and .alpha. are functions of temperature, and the decay can be accelerated by heat treatment. As a consequence, the extent of decay can be determined for arbitrary time and temperature and, significantly, an appropriate heat treatment can be scheduled for making a device stable within predeterminable limits.
    Type: Grant
    Filed: December 4, 1995
    Date of Patent: April 15, 1997
    Assignee: Lucent Technologies Inc.
    Inventors: Turan Erdogan, Paul J. Lemaire, Victor Mizrahi, Donald P. Monroe
  • Patent number: 5442205
    Abstract: A heterostructure includes a stained epitaxial layer of either silicon or germanium that is located overlying a silicon substrate, with a spatially graded Ge.sub.x Si.sub.1-x epitaxial layer overlain by a ungraded Ge.sub.x.sbsb.0 Si.sub.1-x.sbsb.0 intervening between the silicon substrate and the strained layer. Such a heterostructure can serve as a foundation for such devices as surface emitting LEDs, either n-channel or p-channel silicon-based MODFETs, and either n-channel or p-channel silicon-based MOSFETs.
    Type: Grant
    Filed: August 9, 1993
    Date of Patent: August 15, 1995
    Assignee: AT&T Corp.
    Inventors: Daniel Brasen, Eugene A. Fitzgerald, Jr., Martin L. Green, Donald P. Monroe, Paul J. Silverman, Ya-Hong Xie