Patents by Inventor Donald W. Oxley
Donald W. Oxley has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 5394537Abstract: A virtual memory system groups pages into clusters according to use, determined by first reference and frequency of reference. The virtual memory system comprises a random access memory and an auxiliary memory. A central processing unit the virtual memory system with an address. Whenever that address identifies a memory location not stored in the RAM, the entire cluster of pages in which the address is located is retrieved from the auxiliary memory into the random access memory.Type: GrantFiled: October 1, 1993Date of Patent: February 28, 1995Assignee: Texas Instruments IncorporatedInventors: Howard R. Courts, Donald W. Oxley
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Patent number: 4989137Abstract: A computer memory system for use with a user processor provides automatic memory operations independently of the user processor. The memory system includes a logical memory system which is accessed by the user processor through a binding register unit, enabling the user processor to allocate blocks and specify the length of the blocks. Data within the blocks can also be specified by the user by relative indexing with respect to a block specifier in the binding register unit. The user cannot access the memory directly, but must access the memory through the binding registers. The logical memory system is controlled by a separate memory management unit which manages the physical memory of the system and which manages the memory to have the logical memory system appearance to the user processor.Type: GrantFiled: July 12, 1984Date of Patent: January 29, 1991Assignee: Texas Instruments IncorporatedInventors: Donald W. Oxley, Glenn E. Manuel, William M. Knight, Jr., Jeri J. Loafman
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Patent number: 4985829Abstract: A cache hierarchy to be managed by a memory management unit (MMU) combines the advantages of logical and virtual address caches by providing a cache hierarchy having a logical address cache backed up by a virtual address cache to achieve the performance advantage of a large logical address cache, and the flexibility and efficient use of cache capacity of a large virtual address cache. A physically small logical address cache is combined with a large virtual address cache. The provision of a logical address cache enables reference count management to be done completely by the controller of the virtual address cache and the memory management processor in the MMU. Since the controller of the logical address cache is not involved in the overhead associated with reference counting, higher performance is accomplished as the CPU-MMU interface is released as soon as the access to the logical address cache is completed.Type: GrantFiled: June 26, 1987Date of Patent: January 15, 1991Assignee: Texas Instruments IncorporatedInventors: Satish M. Thatte, Donald W. Oxley
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Patent number: 4853842Abstract: A uniform memory system for use with symbolic computers has a very large virtual address space. No separate files, not directly addressable in the address space of the virtual memory, exist. A special object, the peristent root, defines memory objects which are relatively permanent, such objects being traceable by pointers from the persistent root. A tombstone mechanism is used to prevent objects from referencing deleted objects.Type: GrantFiled: February 19, 1988Date of Patent: August 1, 1989Assignee: Texas Instruments IncorporatedInventors: Satish M. Thatte, Donald W. Oxley
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Patent number: 4797810Abstract: An incremental garbage collector for use in conjunction with a virtual memory, operates on selected generations of an area upon objects which are contained in a semispace, oldspace or newspace, and during the garbage collection process, all accessible objects are copied from the oldspace to the newspace. The garbage collection process occurs in four phases. In the "flip" phase oldspace and newspace of each generation are exchanged. In the "trace" phase, the pointers which are part of a root set of the generation being collected are traced and all oldspace objects referenced by the pointers are copied to newspace, and the pointers in the root set are updated. All copied objects are then "scavenged" to update any pointers in the cells of the copied objects, and to copy to newspace all oldspace objects referenced by those pointers. Finally a "cleaning oldspace" phase is performed as a low-priority background process to purge the entries for the virtual pages on which "obsolete" pointers reside.Type: GrantFiled: June 26, 1986Date of Patent: January 10, 1989Assignee: Texas Instruments IncorporatedInventors: Timothy J. McEntee, Robert W. Bloemer, Donald W. Oxley, Satish M. Thatte
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Patent number: 4775932Abstract: A memory system for association with a user processor for operation independently from the user processor includes a physical memory and an interface unit for enabling the associated user processor to access the physical memory. The physical memory is represented in a virtual address space which is garbage collected in parallel with the operation of the user processor. The garbage collection process includes reference count deallocation and a garbage collection algorithm for deallocating cyclic structures not deallocated by the reference count process. The reference count process includes providing for a reference count indicating the number of pointer references to a memory block in the virtual address space. When the reference count becomes zero, and no other references to a memory block exist, the block may be freed. In the garbage collection algorithm, the virtual memory space is traced in areas, called OLDSPACE, and compactly copied into a new area, called NEWSPACE.Type: GrantFiled: July 31, 1984Date of Patent: October 4, 1988Assignee: Texas Instruments IncorporatedInventors: Donald W. Oxley, Timothy J. McEntee, Satish M. Thatte
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Patent number: 4758944Abstract: A pointer, N, indicates an address in a virtual memory space of a demand paged memory including a plurality of virtual address pages and a fixed number of physical memory pages into which blocks of information can be written. A back-up memory store is provided for containing paged-out memory pages. The pointer, N, is advanced along the virtual address pages to indicate the next available virtual address page for allocation, and newly allocated blocks are located on the virtual address page pointed to by said pointer N. Should the necessary space for a block allocation not exist on the page pointed to by said pointer, N, a page which is most recently used and least sparsely utilized is identified from the physical pages onto which blocks have been previously written the block is allocated on that page. If no space remains on the virtual address pages in physical memory for block allocation, then, a least recently used and most sparsely allocated page is identified and paged-out to the back-up store.Type: GrantFiled: August 24, 1984Date of Patent: July 19, 1988Assignee: Texas Instruments IncorporatedInventors: David H. Bartley, Timothy J. McEntee, Donald W. Oxley
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Patent number: 4757438Abstract: A computer system is provided which enables automatic memory operations independently of a CPU. The computer system includes a virtual machine and a logical memory system which is accessed by the virtual machine through a binding register unit, enabling the virtual machine to allocate blocks and specify the length of the blocks. Data within the blocks can also be specified by the user by relative indexing with respect to a block specifier in the binding register unit. The logical memory system is controlled by a separate memory management unit which manages the physical memory of the system and which manages the memory to have the logical memory system appearance to the virtual machine.Type: GrantFiled: July 12, 1984Date of Patent: July 12, 1988Assignee: Texas Instruments IncorporatedInventors: Satish Thatte, Donald W. Oxley
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Patent number: 4716524Abstract: A reference count decimator and method of operating a computer system includes a decimator queue for containing indications of pointer reference count increments. Apparatus is provided for determining if a referencing event would cause a decrement of a reference count, and for searching the decimator queue to determine if a counterpart of the reference event exists in the queue, to thereby define an increment/decrement pair. If an increment/decrement pair is determined to exist in the queue, the increment/decrement pair is cancelled from the queue so that the increment/decrement point reference pairs are removed from the computer system without actually modifying the reference count indications associated with the memory blocks.Type: GrantFiled: April 4, 1985Date of Patent: December 29, 1987Assignee: Texas Instruments IncorporatedInventors: Donald W. Oxley, David H. Bartley, Timothy J. McEntee
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Patent number: 4695949Abstract: A method and apparatus for managing a block oriented memory of the type in which each memory block has an associated reference count representing the number of pointers to it from other memory blocks and itself. Efficient and cost-effective implementation of reference counting alleviates the need for frequent garbage collection, which is an expensive operation. The apparatus includes a hash table into which the virtual addresses of blocks of memory which equal zero are maintained. When the reference count of a block increases from zero, its virtual address is removed from the table. When the reference count of a block decreases to zero, its virtual address is inserted into the table. When the table is full, a reconciliation operation is performed to identify those addresses which are contained in a set of binding registers associated with the CPU, and any address not contained in the binding registers are evacuated into a garbage buffer for subsequent garbage collection operations.Type: GrantFiled: July 19, 1984Date of Patent: September 22, 1987Assignee: Texas Instruments IncorporatedInventors: Satish Thatte, Donald W. Oxley
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Patent number: 4660130Abstract: A method for compacting blocks of memory in a demand paged virtual address space which includes a plurality of virtual address pages includes identifying active and stable blocks to be compacted by defining a pointer to indicate a page of the virtual memory space, and advancing the pointer to continually indicate the page of the beginning of the available virtual memory space. As new blocks are allocated, they are located in the virtual address space beginning at the next available location of the advancing pointer. As blocks are referenced by the user, they are moved to the current location of the advancing pointer, so that, stable blocks may be collected together on stable pages and active blocks are collected together on active pages. A disk memory is provided, and periodically the pages containing collected stable blocks are "paged-out" to it.Type: GrantFiled: July 24, 1984Date of Patent: April 21, 1987Assignee: Texas Instruments IncorporatedInventors: David H. Bartley, Timothy J. McEntee, Donald W. Oxley, Satish M. Thatte