Patents by Inventor Donald W. Plass

Donald W. Plass has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190228812
    Abstract: Embodiments include a method, memory system and a device for the operating a bit-line sensing circuit for bias-controlled bit-line sensing, the embodiments include an input for receiving a single-ended local bit-line signal, a pass device having a first terminal coupled to the input and a second terminal connected to a global bit-line node, The embodiments also include a first inverter having an input connected to the global bit-line node, a header circuit coupled to the first inverter and a first direct current (DC) bias circuit, and a footer circuit coupled to the first inverter and a second DC bias circuit. The embodiments include a second gated inverter having an input coupled to an output of the first inverter.
    Type: Application
    Filed: January 19, 2018
    Publication date: July 25, 2019
    Inventors: Abraham Mathews, Donald W. Plass
  • Patent number: 9748958
    Abstract: A driver circuit and associated techniques include managing voltage driving an electronic device. An input signal having a first voltage level is received. Processes may perform level shifting of the first voltage level to a second voltage level. The second voltage level may be clamped, for instance, but a diode circuit. The second output voltage level may be programmable, as may be current and resistance levels of the driver circuit.
    Type: Grant
    Filed: February 24, 2016
    Date of Patent: August 29, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Gregory J. Fredeman, Abraham Mathews, Donald W. Plass, Kenneth J. Reyer
  • Publication number: 20160352336
    Abstract: A driver circuit and associated techniques include managing voltage driving an electronic device. An input signal having a first voltage level is received. Processes may perform level shifting of the first voltage level to a second voltage level. The second voltage level may be clamped, for instance, but a diode circuit. The second output voltage level may be programmable, as may be current and resistance levels of the driver circuit.
    Type: Application
    Filed: February 24, 2016
    Publication date: December 1, 2016
    Inventors: Gregory J. Fredeman, Abraham Mathews, Donald W. Plass, Kenneth J. Reyer
  • Patent number: 9341655
    Abstract: A method for operating a charge pump that supplies switching current for a plurality of transistors includes a capacitor generating a pumped voltage. A comparator generates a pump control signal for turning on and off charging of the pump capacitor based on a difference between a comparison voltage and a reference voltage. A direct voltage sensor receives a feedback signal reflecting the pumped voltage and generates the comparison voltage in response to the feedback signal. The sensor includes a sensor resistor, a current source configured to drive a sensor current through the sensor resistor, and a differential op-amp that drives the sensor current to cause the voltage drop across the sensor resistor to remain constant as the pumped voltage experiences the voltage drop. The charge pump may include two similar direct voltage sensor controlling positive and negative pumped voltages.
    Type: Grant
    Filed: September 30, 2014
    Date of Patent: May 17, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Paul D. Muench, Donald W. Plass, Michael A. Sperling
  • Patent number: 9299458
    Abstract: A method for testing a circuit comprising a memory element, a voltage comparator and a supply selector, the circuit is configured to be connected to two power supplies, the voltage comparator is configured to provide an output indicative of a voltage difference between the two power supplies above a predetermined threshold, the supply selector is configured to select a power supply to feed power to the memory element in response to the output from the voltage comparator. The method comprises connecting the two power supplies to the circuit, wherein said connecting comprises causing the two power supplies to drive power to the memory element and to another element of the circuit, wherein the voltage different between the two power supplies is above the predetermined threshold.
    Type: Grant
    Filed: September 23, 2015
    Date of Patent: March 29, 2016
    Assignee: International Business Machines Corporation
    Inventors: Lior Binyamini, Lidar Herooti, Noam Jungmann, Elazar Kachir, Donald W. Plass, Hezi Shalom, Israel Wagner
  • Publication number: 20160071617
    Abstract: A method for testing a circuit comprising a memory element, a voltage comparator and a supply selector, the circuit is configured to be connected to two power supplies, the voltage comparator is configured to provide an output indicative of a voltage difference between the two power supplies above a predetermined threshold, the supply selector is configured to select a power supply to feed power to the memory element in response to the output from the voltage comparator. The method comprises connecting the two power supplies to the circuit, wherein said connecting comprises causing the two power supplies to drive power to the memory element and to another element of the circuit, wherein the voltage different between the two power supplies is above the predetermined threshold.
    Type: Application
    Filed: September 23, 2015
    Publication date: March 10, 2016
    Inventors: Lior Binyamini, Lidar Herooti, Noam Jungmann, Elazar Kachir, Donald W. Plass, Hezi Shalom, Israel Wagner
  • Publication number: 20160071551
    Abstract: A circuit comprising a first power supply having a first voltage and a second power supplying having a second voltage, wherein said first and second voltages are different at least in some cycles of said circuit, a memory element, wherein said first and second power supplies are driven into said memory element, a voltage comparator having connected thereto said first and second power supplies, wherein said voltage comparator is an analog to digital converter configured to provide digital output indicting of a voltage difference over a predetermined threshold between said first and second power supplies, and a supply selector element, wherein said supply selector element is configured to disconnect said second power supply from said memory element in response to the digital output of said voltage comparator.
    Type: Application
    Filed: September 4, 2014
    Publication date: March 10, 2016
    Inventors: Lior Binyamini, Lidar Herooti, Noam Jungmann, Elazar Kachir, Donald W. Plass, Hezi Shalom, Israel Wagner
  • Patent number: 9263096
    Abstract: A circuit comprising a first power supply having a first voltage and a second power supplying having a second voltage, wherein said first and second voltages are different at least in some cycles of said circuit, a memory element, wherein said first and second power supplies are driven into said memory element, a voltage comparator having connected thereto said first and second power supplies, wherein said voltage comparator is an analog to digital converter configured to provide digital output indicting of a voltage difference over a predetermined threshold between said first and second power supplies, and a supply selector element, wherein said supply selector element is configured to disconnect said second power supply from said memory element in response to the digital output of said voltage comparator.
    Type: Grant
    Filed: September 4, 2014
    Date of Patent: February 16, 2016
    Assignee: International Business Machines Corporation
    Inventors: Lior Binyamini, Lidar Herooti, Noam Jungmann, Elazar Kachir, Donald W. Plass, Hezi Shalom, Israel Wagner
  • Patent number: 9250271
    Abstract: Embodiments relate to a direct voltage sensor and a charge pump system for a computer system. A charge pump that supplies switching current for a plurality of transistors includes a capacitor generating a pumped voltage. A comparator generates a pump control signal for turning on and off charging of the pump capacitor based on a difference between a comparison voltage and a reference voltage. A direct voltage sensor receives a feedback signal reflecting the pumped voltage and generates the comparison voltage in response to the feedback signal. The sensor includes a sensor resistor, a current source configured to drive a sensor current through the sensor resistor, and a differential op-amp that drives the sensor current to cause the voltage drop across the sensor resistor to remain constant as the pumped voltage experiences the voltage drop. The charge pump may include two similar direct voltage sensor controlling positive and negative pumped voltages.
    Type: Grant
    Filed: August 26, 2013
    Date of Patent: February 2, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Paul D. Muench, Donald W. Plass, Michael A. Sperling
  • Patent number: 9224437
    Abstract: A single-ended input sense amplifier uses a pass device to couple the input local bit-line to a global bit-line evaluation node. The sense amplifier also includes a pair of cross-coupled inverters, a first inverter of which has an input that coupled directly to the global bit-line evaluation node. The output of the second inverter is selectively coupled to the global bit-line evaluation node in response to a control signal, so that when the pass device is active, the local bit line charges or discharges the global bit-line evaluation node without being affected substantially by a state of the output of the second inverter. When the control signal is in the other state, the cross-coupled inverter forms a latch. An internal output control circuit of the second inverter interrupts the feedback provided by the second inverter in response to the control signal.
    Type: Grant
    Filed: October 31, 2013
    Date of Patent: December 29, 2015
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: John E. Barth, Jr., Abraham Mathews, Donald W. Plass, Kenneth J. Reyer
  • Patent number: 9099200
    Abstract: A novel and useful SRAM restore tracking circuit adapted to improve the tracking of SRAM cell behavior for different PVT corners. The SRAM array access path is mainly influenced by two stages: (1) the wordline (WL) delay and (2) the SRAM cell delay. These two stages are usually the most sensitive for process variation in the memory access path. The restore tracking circuit incorporates two novel topologies for enhanced tracking to SRAM cell behavior. The first topology is a circuit that functions to mimic the wordline load and delay characteristics. The WL stage is very sensitive to process variation due to the large load it must drive and the usually relatively poor slope (i.e. depending on the number of cells the WL). The second topology is a circuit that mimics the SRAM cell load and delay characteristics. The SRAM cell is very sensitive to process variation due to its very small device features and the high number of cells in the memory array.
    Type: Grant
    Filed: June 27, 2013
    Date of Patent: August 4, 2015
    Assignee: International Business Machines Corporation
    Inventors: Lior Binyamini, Noam Jungmann, Elazar Kachir, Donald W. Plass
  • Publication number: 20150162059
    Abstract: A method of operation of a high-voltage word-line driver circuit for a memory device prevents any single transistor of the driver from having the full power supply voltage from which the word-line output signal is generated, from being applied across any single transistor of the word-line driver circuit. A pair of cascode devices are connected in series with the pull-down device of the input stage and a pull-up device of the input stage, and biased using reference voltages to control the maximum voltage drop across the pull-down device when the pull-down device is off and the pull-up device is active, and to control the maximum voltage drop across the pull-up device when the pull-down device is active. The output stage also includes cascode devices that protect the output pull-down and pull-up devices, and the reference voltages that bias the input and output cascode pairs may be the same reference voltages.
    Type: Application
    Filed: June 10, 2014
    Publication date: June 11, 2015
    Inventors: Gregory J. Fredeman, Abraham Mathews, Donald W. Plass, Kenneth J. Reyer
  • Patent number: 9053770
    Abstract: A method of operation of a high-voltage word-line driver circuit for a memory device prevents any single transistor of the driver from having the full power supply voltage from which the word-line output signal is generated, from being applied across any single transistor of the word-line driver circuit. A pair of cascode devices are connected in series with the pull-down device of the input stage and a pull-up device of the input stage, and biased using reference voltages to control the maximum voltage drop across the pull-down device when the pull-down device is off and the pull-up device is active, and to control the maximum voltage drop across the pull-up device when the pull-down device is active. The output stage also includes cascode devices that protect the output pull-down and pull-up devices, and the reference voltages that bias the input and output cascode pairs may be the same reference voltages.
    Type: Grant
    Filed: June 10, 2014
    Date of Patent: June 9, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Gregory J. Fredeman, Abraham Mathews, Donald W. Plass, Kenneth J. Reyer
  • Patent number: 9047930
    Abstract: A single-ended low-swing power-savings mechanism is provided. The mechanism comprises a precharge device that turns off in an evaluation phase and a first biasing device is always on. Within the mechanism, a strength of a keeper device is changed to a first level in response to an input of the second biasing device being at a first voltage level. Within the mechanism the strength of the keeper device is changed to a second level in response to the input of the second biasing device being at a second voltage level. Responsive to receiving a (precharged voltage level read data line signal, a precharged voltage level of the first node falls faster when the keeper device is weakened to a first level. The keeper device turns on in response to receiving a LOW signal and pulls up the voltage at the first node so that a HIGH signal is output.
    Type: Grant
    Filed: July 26, 2013
    Date of Patent: June 2, 2015
    Assignee: International Business Machines Corporation
    Inventors: Gregory J. Fredeman, Abraham Mathews, Donald W. Plass, Vinod Ramadurai
  • Patent number: 9025403
    Abstract: A high-voltage word-line driver circuit for a memory device uses cascode devices to prevent any single transistor of the driver circuit from having the full power supply voltage from which the word-line output signal is generated, from being applied across any single transistor of the word-line driver circuit. A pair of cascode devices are connected in series with the pull-down device of the input stage and a pull-up device of the input stage, and biased using reference voltages to control the maximum voltage drop across the pull-down device when the pull-down device is off and the pull-up device is active, and to control the maximum voltage drop across the pull-up device when the pull-down device is active. The output stage also includes cascode devices that protect the output pull-down and pull-up devices, and the reference voltages that bias the input and output cascode pairs may be the same reference voltages.
    Type: Grant
    Filed: December 6, 2013
    Date of Patent: May 5, 2015
    Assignee: International Business Machines Corporation
    Inventors: Gregory J. Fredeman, Abraham Mathews, Donald W. Plass, Kenneth J. Reyer
  • Publication number: 20150117120
    Abstract: A single-ended input sense amplifier uses a pass device to couple the input local bit-line to a global bit-line evaluation node. The sense amplifier also includes a pair of cross-coupled inverters, a first inverter of which has an input that coupled directly to the global bit-line evaluation node. The output of the second inverter is selectively coupled to the global bit-line evaluation node in response to a control signal, so that when the pass device is active, the local bit line charges or discharges the global bit-line evaluation node without being affected substantially by a state of the output of the second inverter. When the control signal is in the other state, the cross-coupled inverter forms a latch. An internal output control circuit of the second inverter interrupts the feedback provided by the second inverter in response to the control signal.
    Type: Application
    Filed: October 31, 2013
    Publication date: April 30, 2015
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: John E. Barth, JR., Abraham Mathews, Donald W. Plass, Kenneth J. Reyer
  • Publication number: 20150054572
    Abstract: A method for operating a charge pump that supplies switching current for a plurality of transistors includes a capacitor generating a pumped voltage. A comparator generates a pump control signal for turning on and off charging of the pump capacitor based on a difference between a comparison voltage and a reference voltage. A direct voltage sensor receives a feedback signal reflecting the pumped voltage and generates the comparison voltage in response to the feedback signal. The sensor includes a sensor resistor, a current source configured to drive a sensor current through the sensor resistor, and a differential op-amp that drives the sensor current to cause the voltage drop across the sensor resistor to remain constant as the pumped voltage experiences the voltage drop. The charge pump may include two similar direct voltage sensor controlling positive and negative pumped voltages.
    Type: Application
    Filed: September 30, 2014
    Publication date: February 26, 2015
    Inventors: Paul D. Muench, Donald W. Plass, Michael A. Sperling
  • Publication number: 20150054493
    Abstract: Embodiments relate to a direct voltage sensor and a charge pump system for a computer system. A charge pump that supplies switching current for a plurality of transistors includes a capacitor generating a pumped voltage. A comparator generates a pump control signal for turning on and off charging of the pump capacitor based on a difference between a comparison voltage and a reference voltage. A direct voltage sensor receives a feedback signal reflecting the pumped voltage and generates the comparison voltage in response to the feedback signal. The sensor includes a sensor resistor, a current source configured to drive a sensor current through the sensor resistor, and a differential op-amp that drives the sensor current to cause the voltage drop across the sensor resistor to remain constant as the pumped voltage experiences the voltage drop. The charge pump may include two similar direct voltage sensor controlling positive and negative pumped voltages.
    Type: Application
    Filed: August 26, 2013
    Publication date: February 26, 2015
    Applicant: International Business Machines Corporation
    Inventors: Paul D. Muench, Donald W. Plass, Michael A. Sperling
  • Publication number: 20150029803
    Abstract: A single-ended low-swing power-savings mechanism is provided. The mechanism comprises a precharge device that turns off in an evaluation phase and a first biasing device is always on. Within the mechanism, a strength of a keeper device is changed to a first level in response to an input of the second biasing device being at a first voltage level. Within the mechanism the strength of the keeper device is changed to a second level in response to the input of the second biasing device being at a second voltage level. Responsive to receiving a (precharged voltage level read data line signal, a precharged voltage level of the first node falls faster when the keeper device is weakened to a first level. The keeper device turns on in response to receiving a LOW signal and pulls up the voltage at the first node so that a HIGH signal is output.
    Type: Application
    Filed: July 26, 2013
    Publication date: January 29, 2015
    Applicant: International Business Machines Corporation
    Inventors: Gregory J. Fredeman, Abraham Mathews, Donald W. Plass, Vinod Ramadurai
  • Patent number: 8937840
    Abstract: A digital voltage boost circuit, optionally working in parallel with an analog voltage regulator, periodically injects a constant amount of current each cycle into the bit line of a high density memory array to eliminate the bias voltage reduction which would otherwise occur. This results in a much faster recovery time and reduces the semiconductor real estate required. A pulse generator in the boost circuit generates one or more current modulation signals which control corresponding current supply devices in a current source. The boost circuit drives a constant amount of current to the bias voltage node each memory cycle.
    Type: Grant
    Filed: December 15, 2011
    Date of Patent: January 20, 2015
    Assignee: International Business Machines Corporation
    Inventors: James W. Dawson, Noam Jungmann, Elazar Kachir, Udi Nir, Donald W. Plass