Abstract: A positive electrode active material includes a lithium composite transition metal oxide represented by Formula 1 described in the present specification and satisfies Equation (1) described in the present specification, wherein an average particle diameter D50 of a secondary particle is in a range of 1 µm to 8 µm. A method of preparing the same, and a positive electrode material including the same are also provided.

Abstract: A memory device includes: a memory cell array including a first memory cell group including memory cells located within a first physical distance from a reference node and a second memory cell group including memory cells located beyond the first physical distance from the reference node; a peripheral circuit configured to perform a program operation of applying program voltages increasing gradually to memory cells included in the memory cell array through word lines; and control logic configured to determine a time at which a first program permission voltage is applied to the first memory cell group and determine a magnitude of the first program permission voltage on the basis of a magnitude of the program voltages in response to a gradual increase in the program voltages, the control logic is further configured to control the peripheral circuit to apply the first program permission voltage to the first memory cell group through bit lines.

Abstract: A method of operating a semiconductor memory device includes starting a program operation on selected memory cells using a main verification voltage and an auxiliary verification voltage in response to a program command, receiving a program suspend command during the program operation, and changing at least one auxiliary voltage verification result information among threshold voltage states which are not program-passed to at least one data pattern among threshold voltage states which program-passed, in response to the program suspend command.

Abstract: A memory device includes a plurality of memory cells, where each memory cell is configured to be in an erased state or one of a plurality of program states according to data stored therein. The memory device also includes a peripheral circuit configured to, in a program operation on the plurality of memory cells, perform a first program voltage application operation on first memory cells, the first memory cells being to be programmed to first respective program states. The peripheral circuit is also configured to perform, after the first program voltage application operation, a pre-program voltage application operation on second memory cells, the second memory cells being to be programmed to second respective program states.

Abstract: A method of operating a semiconductor memory device includes starting a program operation on selected memory cells using a main verification voltage and an auxiliary verification voltage in response to a program command, receiving a program suspend command during the program operation, and changing at least one auxiliary voltage verification result information among threshold voltage states which are not program-passed to at least one data pattern among threshold voltage states which program-passed, in response to the program suspend command.

Abstract: A method of operating a non-volatile memory device includes performing a first sensing operation on the non-volatile memory device during a first sensing time including a first section, a second section, and a third section. The performing of the first sensing operation includes applying a first voltage level, which is variable according to a first target voltage level, to a selected word line in the first section, applying a second voltage level, which is different from the first voltage level, to the selected word line in the second section, and applying the first target voltage level, which is different from the second voltage level, to the selected word line in the third section. The first voltage level becomes greater as the first target voltage level becomes greater.

Abstract: Provided herein may be a memory device and a method of operating the same. The memory device may include a plurality of memory cells, a program operation performer configured to perform a plurality of program loops on the plurality of memory cells, a step voltage calculator configured to calculate a step voltage, the step voltage being a difference of magnitude between program voltages that are applied in any two consecutive program loops, a reference bit determiner configured to determine a reference number of fail bits based on a magnitude of the step voltage, and a verification result generator configured to generate verification result information based on a result of a comparison between the reference number of fail bits and a number of on-cells, among the plurality of memory cells, identified in a verify operation that is included in a program loop, among the plurality of program loops.

Abstract: A method of operating a non-volatile memory device includes performing a first sensing operation on the non-volatile memory device during a first sensing time including a first section, a second section, and a third section. The performing of the first sensing operation includes applying a first voltage level, which is variable according to a first target voltage level, to a selected word line in the first section, applying a second voltage level, which is different from the first voltage level, to the selected word line in the second section, and applying the first target voltage level, which is different from the second voltage level, to the selected word line in the third section. The first voltage level becomes greater as the first target voltage level becomes greater.

Abstract: A semiconductor memory device includes a plurality of memory blocks and a contact region. Each of the plurality of memory blocks includes a plurality of memory cells. The contact region is formed between the plurality of memory blocks. The semiconductor memory device uses a first memory block that is not adjacent to the contact region and a second memory block adjacent to the contact region among the plurality of memory blocks differently.

Abstract: The present disclosure relates to an electronic device. A memory device includes a plurality of memory cells coupled to a plurality of word lines, a voltage generator generating program-related voltages to be applied to the plurality of word lines, an address decoder transferring the program-related voltages to the plurality of word lines, and an operation controller controlling the voltage generator and the address decoder to apply a program voltage to a selected word line among the plurality of word lines, a second pass voltage to adjacent word lines neighboring the selected word line, a first pass voltage to remaining word lines except for the selected word line and the adjacent word lines, and to apply a ground voltage to the selected word line and the first pass voltage to the adjacent word lines during a first period.

Abstract: A memory device includes: a plurality of memory cells; a peripheral circuit for performing a program operation including a plurality of loops each including a program voltage apply step and a verify step by using a plurality of verify voltages; and a program operation controller for controlling the peripheral circuit to perform the program operation. The program operation controller includes: a verify voltage controller for changing a verify voltage interval as an interval between the plurality of verify voltages from a predetermined target loop among the plurality of loops; and a bit line voltage controller to control bit line voltages applied to bit lines connected to first memory cells and second memory cells in the program voltage apply steps of an (n+1)th loop and an (n+2)th loop, based on a verify result in the verify step of an nth loop among the plurality of loops.

Abstract: A memory device and method of operation includes memory cells and a program operation performer configured to perform a verify operation and a program voltage apply operation, wherein the verify operation verifies whether threshold voltages of the memory cells have reached threshold voltages corresponding to a target program state using a first verify voltage, a second verify voltage higher than the first verify voltage and a third verify voltage higher than the second verify voltage, and the program voltage apply operation applies a program voltage to a word line. The memory device and method of operation also includes a program operation controller configured to control the program operation performer such that, during the program voltage apply operation, a precharge voltage is first applied to a second bit line coupled to a second memory cell before a precharge voltage is applied to a first bit line.

Abstract: A method of operating a non-volatile memory device includes performing a first sensing operation on the non-volatile memory device during a first sensing time including a first section, a second section, and a third section. The performing of the first sensing operation includes applying a first voltage level, which is variable according to a first target voltage level, to a selected word line in the first section, applying a second voltage level, which is different from the first voltage level, to the selected word line in the second section, and applying the first target voltage level, which is different from the second voltage level, to the selected word line in the third section. The first voltage level becomes greater as the first target voltage level becomes greater.

Abstract: An electronic device, and more particularly, a page buffer is provided. The page buffer includes a sensing node configured to sense a potential of a bit line coupled to a memory cell, a precharging circuit coupled to the sensing node and configured to precharge a potential of the sensing node to a first voltage during an evaluation operation on the memory cell, a discharging circuit coupled to the sensing node and configured to discharge the potential of the sensing node from the first voltage to a second voltage, and a latch circuit coupled to the discharging circuit and configured to store therein data sensed from the memory cell based on a result of comparing the potential of the sensing node with a reference voltage after the potential of the sensing node is discharged to the second voltage and a predetermined period elapses.

Abstract: A memory device includes a memory structure including at least one non-volatile memory cell capable of storing multi-bit data, and a control device configured to perform a program verification after a first program pulse is applied to the at least one non-volatile memory cell, determine a program mode for the at least one non-volatile memory cell based on a result of the program verification, and change a level of a pass voltage, applied to another non-volatile memory cell coupled to the at least one non-volatile memory cell, from a first level to a second level which is higher than the first level, or a setup time for changing a potential of a bit line coupled to the at least one non-volatile memory cell, according to the program mode.

Abstract: A nonvolatile memory device includes a memory cell array and a row decoder. The memory cell array includes a plurality of mats. A first cell string of first mat is connected to a plurality of first word-lines, a first bit-line and a first string selection line. A second cell string of second mat is connected to a plurality of second word-lines, a second bit-line and a second string selection line. Each of the first and second cell strings includes a ground selection transistor, memory cells, and a string selection transistor coupled in series. The row decoder applies a first voltage to a third word-line among the plurality of first and second word-lines for a first period of time in a single mat mode and to apply a second voltage to the third word-line for a second period of time longer than the first period of time in a multi-mat mode.

Abstract: Provided herein may be a memory device and a method of operating the same. The memory device may include a plurality of memory cells coupled between a common source line and a bit line, a peripheral circuit configured to perform a plurality of program loops, each including a program voltage application operation of applying a program voltage to a selected memory cell and a verify operation of verifying a program state of the selected memory cell, and a control logic configured to control, at the program voltage application operation, the peripheral circuit to apply a precharge voltage to the common source line and change at least one of a magnitude of the precharge voltage and a time during which the precharge voltage is applied, depending on a magnitude of the program voltage.

Abstract: A method of operating a non-volatile memory device includes performing a first sensing operation on the non-volatile memory device during a first sensing time including a first section, a second section, and a third section. The performing of the first sensing operation includes applying a first voltage level, which is variable according to a first target voltage level, to a selected word line in the first section, applying a second voltage level, which is different from the first voltage level, to the selected word line in the second section, and applying the first target voltage level, which is different from the second voltage level, to the selected word line in the third section. The first voltage level becomes greater as the first target voltage level becomes greater.

Abstract: A memory device includes a controller that performs a program verification after a first program pulse is applied to the at least one non-volatile memory cell. The first program pulse is applied during a data program operation and the data program operation includes applying program pulses to program multi-bit data to the at least one non-volatile memory cell. The controller also determines a program mode for the at least one non-volatile memory cell based on a result of the program verification, and changes at least one of a level of a first control voltage based on the program mode. The first control voltage is applied to a drain select line coupled to the at least one non-volatile memory cell.

Abstract: An operating method of a memory device, comprises: a program operation of applying a program voltage to a selected word line to program selected memory cells connected to the selected word line, a first verification operation of applying a first verification voltage to the selected word line and applying a first verification pass voltage to unselected word lines to verify a first program state of the selected memory cells, and a second verification operation of applying a second verification voltage to the selected word line and applying a second verification pass voltage to the unselected word lines to verify a second program state higher than the first program state.