Patents by Inventor Dong-Hyuk Chae

Dong-Hyuk Chae has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220384673
    Abstract: A method for manufacturing a light emitting element includes forming a first semiconductor structure including a first semiconductor layer doped with a first conductivity type dopant disposed on a base substrate, a light emitting layer disposed on the first semiconductor layer, and a second semiconductor layer disposed on the light emitting layer and doped with a second conductivity type dopant; forming a second semiconductor structure spaced apart from another second semiconductor structure on the base substrate by etching the first semiconductor structure in a direction perpendicular to a surface of the base substrate; and activating a second conductivity type dopant in the second semiconductor layer of the second semiconductor structure to form a light emitting element core.
    Type: Application
    Filed: January 20, 2022
    Publication date: December 1, 2022
    Applicant: Samsung Display Co., LTD.
    Inventors: Ji Song Chae, Joo Hee Lee, Jin Hyuk Jang, Sang Ho Jeon, Si Sung Kim, Dong Eon Lee, Hyung Seok Kim, Jong Jin Lee
  • Publication number: 20220319983
    Abstract: A three-dimensional semiconductor device may comprise a first cell region, a second cell region, and a via plug region disposed between the first cell region and the second cell region; a word line stack disposed in the first cell region, the via plug region, and the second cell region, the word line stack including a plurality of word lines and a plurality of interlayer insulating layers which are alternately stacked; and a plurality of via plugs exclusively connected to the plurality of the word lines, respectively, by vertically penetrating through the word line stack in the via plug region. The via plugs may have an arrangement of a zigzag pattern in a row direction from a top view. The diameters of the via plugs may increase in the row direction.
    Type: Application
    Filed: September 7, 2021
    Publication date: October 6, 2022
    Inventors: Sung Lae OH, Sang Woo PARK, Dong Hyuk CHAE
  • Patent number: 11398443
    Abstract: A memory device having a vertical structure includes a memory cell array defined in a cell wafer, and having a plurality of word lines extending in a first direction and arranged in a second direction, and having a plurality of bit lines extending in the second direction and arranged in the first direction; and a logic circuit configured to control the memory cell array, and including a page buffer low-voltage circuit, a page buffer high-voltage circuit, a row decoder circuit and a peripheral circuit, wherein the page buffer low-voltage circuit is disposed in a first peripheral wafer and the page buffer high-voltage circuit, the row decoder circuit and the peripheral circuit are disposed in a second peripheral wafer, and wherein the cell wafer overlaps with the first peripheral wafer and the second peripheral wafer in a vertical direction that is perpendicular to a plane formed by the first direction and the second direction.
    Type: Grant
    Filed: March 24, 2021
    Date of Patent: July 26, 2022
    Assignee: SK hynix Inc.
    Inventors: Sung Lae Oh, Sang Woo Park, Dong Hyuk Chae, Ki Soo Kim
  • Patent number: 11315639
    Abstract: A memory device includes a cell wafer including a memory cell array; a first logic wafer bonded to one surface of the cell wafer, and including a first logic circuit which controls the memory cell array; and a second logic wafer bonded to the other surface of the cell wafer which faces away from the one surface, and including a second logic circuit which controls the memory cell array.
    Type: Grant
    Filed: November 2, 2020
    Date of Patent: April 26, 2022
    Assignee: SK hynix Inc.
    Inventors: Sung Lae Oh, Sang Woo Park, Dong Hyuk Chae, Ki Soo Kim
  • Publication number: 20220122932
    Abstract: A memory device having a vertical structure includes a memory cell array defined in a cell wafer, and having a plurality of word lines extending in a first direction and arranged in a second direction, and having a plurality of bit lines extending in the second direction and arranged in the first direction; and a logic circuit configured to control the memory cell array, and including a page buffer low-voltage circuit, a page buffer high-voltage circuit, a row decoder circuit and a peripheral circuit, wherein the page buffer low-voltage circuit is disposed in a first peripheral wafer and the page buffer high-voltage circuit, the row decoder circuit and the peripheral circuit are disposed in a second peripheral wafer, and wherein the cell wafer overlaps with the first peripheral wafer and the second peripheral wafer in a vertical direction that is perpendicular to a plane formed by the first direction and the second direction.
    Type: Application
    Filed: March 24, 2021
    Publication date: April 21, 2022
    Inventors: Sung Lae OH, Sang Woo PARK, Dong Hyuk CHAE, Ki Soo KIM
  • Publication number: 20220115357
    Abstract: A memory device includes: a first wafer including a first substrate, a plurality of first electrode layers and a plurality of first interlayer dielectric layers alternately stacked along first vertical channels projecting in a vertical direction on a top surface of the first substrate, and a dielectric stack comprising a plurality of dielectric layers and the plurality of first interlayer dielectric layers alternately stacked on the top surface of the first substrate; and a second wafer disposed on the first wafer, and including a second substrate, and a plurality of second electrode layers that are alternately stacked with a plurality of second interlayer dielectric layers along second vertical channels projecting in the vertical direction on a bottom surface of the second substrate and have pad parts overlapping with the dielectric stack in the vertical direction.
    Type: Application
    Filed: December 18, 2021
    Publication date: April 14, 2022
    Inventors: Sung Lae OH, Ki Soo KIM, Sang Woo PARK, Dong Hyuk CHAE
  • Patent number: 11239209
    Abstract: A memory device includes a first memory block defined in a first wafer; and a second memory block defined in a second wafer that is disposed in a vertical direction with respect to the first wafer. A size of the first memory block is smaller than a size of the second memory block.
    Type: Grant
    Filed: October 22, 2020
    Date of Patent: February 1, 2022
    Assignee: SK hynix Inc.
    Inventors: Sung Lae Oh, Ki Soo Kim, Sang Woo Park, Dong Hyuk Chae
  • Publication number: 20210384160
    Abstract: A memory device includes a first memory block defined in a first wafer; and a second memory block defined in a second wafer that is disposed in a vertical direction with respect to the first wafer. A size of the first memory block is smaller than a size of the second memory block.
    Type: Application
    Filed: October 22, 2020
    Publication date: December 9, 2021
    Inventors: Sung Lae OH, Ki Soo KIM, Sang Woo PARK, Dong Hyuk CHAE
  • Publication number: 20210383874
    Abstract: A memory device includes a cell wafer including a memory cell array; a first logic wafer bonded to one surface of the cell wafer, and including a first logic circuit which controls the memory cell array; and a second logic wafer bonded to the other surface of the cell wafer which faces away from the one surface, and including a second logic circuit which controls the memory cell array.
    Type: Application
    Filed: November 2, 2020
    Publication date: December 9, 2021
    Inventors: Sung Lae OH, Sang Woo PARK, Dong Hyuk CHAE, Ki Soo KIM
  • Publication number: 20210375901
    Abstract: A memory device is disclosed. The disclosed memory device may include a first wafer, and a second wafer stacked on and bonded to the first wafer. The first wafer may include a cell structure including a memory cell array; and a first logic structure disposed under the cell structure, and including a column control circuit. The second wafer may include a second logic structure including a row control circuit.
    Type: Application
    Filed: October 5, 2020
    Publication date: December 2, 2021
    Inventors: Sung Lae OH, Sang Woo PARK, Dong Hyuk CHAE, Ki Soo KIM
  • Patent number: 11056162
    Abstract: Provided herein is a memory device and a method of operating the same. The memory device may include a memory cell array including a plurality of memory cells, page buffers coupled to the memory cell array through respective bit lines and a control logic configured to control so that, during a read operation, data stored in the memory cell array is sensed and stored in the page buffers, and the data stored in the page buffers is output to an external device, wherein the control logic controls a time point at which a discharge operation is to be performed after the sensing of the data, and a time point at which a data transfer operation between latches included in each of the page buffers is to be performed, in response to a read command received from the external device.
    Type: Grant
    Filed: April 24, 2020
    Date of Patent: July 6, 2021
    Assignee: SK hynix Inc.
    Inventors: Mi Sun Yoon, Dong Hyuk Chae
  • Publication number: 20210166741
    Abstract: Provided herein is a memory device and a method of operating the same. The memory device may include a memory cell array including a plurality of memory cells, page buffers coupled to the memory cell array through respective bit lines and a control logic configured to control so that, during a read operation, data stored in the memory cell array is sensed and stored in the page buffers, and the data stored in the page buffers is output to an external device, wherein the control logic controls a time point at which a discharge operation is to be performed after the sensing of the data, and a time point at which a data transfer operation between latches included in each of the page buffers is to be performed, in response to a read command received from the external device.
    Type: Application
    Filed: April 24, 2020
    Publication date: June 3, 2021
    Inventors: Mi Sun YOON, Dong Hyuk CHAE
  • Publication number: 20210117321
    Abstract: At least one address scheduling method includes selecting a first bit line, selecting a first string connected to the first bit line, performing address scheduling on N pages of each of multi-level cells in the first string sequentially from a bottom word line to a top word line, and after completing the address scheduling on all word lines in the first string, performing address scheduling on second to k-th strings sequentially in the same manner as performed with respect to the first string, where “k” is 2 or a natural number greater than 2.
    Type: Application
    Filed: December 30, 2020
    Publication date: April 22, 2021
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Chi Weon YOON, Dong Hyuk CHAE, Sang-Wan NAM, Jung-Yun YUN
  • Patent number: 10909032
    Abstract: At least one address scheduling method includes selecting a first bit line, selecting a first string connected to the first bit line, performing address scheduling on N pages of each of multi-level cells in the first string sequentially from a bottom word line to a top word line, and after completing the address scheduling on all word lines in the first string, performing address scheduling on second to k-th strings sequentially in the same manner as performed with respect to the first string, where “k” is 2 or a natural number greater than 2.
    Type: Grant
    Filed: April 15, 2020
    Date of Patent: February 2, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chi Weon Yoon, Dong Hyuk Chae, Sang-Wan Nam, Jung-Yun Yun
  • Publication number: 20200242030
    Abstract: At least one address scheduling method includes selecting a first bit line, selecting a first string connected to the first bit line, performing address scheduling on N pages of each of multi-level cells in the first string sequentially from a bottom word line to a top word line, and after completing the address scheduling on all word lines in the first string, performing address scheduling on second to k-th strings sequentially in the same manner as performed with respect to the first string, where “k” is 2 or a natural number greater than 2.
    Type: Application
    Filed: April 15, 2020
    Publication date: July 30, 2020
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Chi Weon YOON, Dong Hyuk CHAE, Sang-Wan NAM, Jung-Yun YUN
  • Patent number: 10671529
    Abstract: At least one address scheduling method includes selecting a first bit line, selecting a first string connected to the first bit line, performing address scheduling on N pages of each of multi-level cells in the first string sequentially from a bottom word line to a top word line, and after completing the address scheduling on all word lines in the first string, performing address scheduling on second to k-th strings sequentially in the same manner as performed with respect to the first string, where “k” is 2 or a natural number greater than 2.
    Type: Grant
    Filed: October 23, 2017
    Date of Patent: June 2, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chi Weon Yoon, Dong Hyuk Chae, Sang-Wan Nam, Jung-Yun Yun
  • Patent number: 10304544
    Abstract: A memory device includes a plurality of memory cells, bit lines connected to the plurality of memory cells, and page buffers coupled to the plurality of memory cells through the bit lines, and performing a read operation on the plurality of memory cells, wherein each of the page buffers comprises: a first latch controlling a bit line precharge operation during the read operation; and a second latch storing a result of a first sensing operation and a result of a second sensing operation performed after the first sensing operation, wherein a value stored in the second latch is inverted when the result of the first sensing operation and the result of second sensing operation are different from each other during the second sensing operation.
    Type: Grant
    Filed: December 8, 2017
    Date of Patent: May 28, 2019
    Assignee: SK hynix Inc.
    Inventors: Hee Joung Park, Kyeong Seung Kang, Won Chul Shin, Dong Hyuk Chae
  • Publication number: 20180322929
    Abstract: A memory device includes a plurality of memory cells, bit lines connected to the plurality of memory cells, and page buffers coupled to the plurality of memory cells through the bit lines, and performing a read operation on the plurality of memory cells, wherein each of the page buffers comprises: a first latch controlling a bit line precharge operation during the read operation; and a second latch storing a result of a first sensing operation and a result of a second sensing operation performed after the first sensing operation, wherein a value stored in the second latch is inverted when the result of the first sensing operation and the result of second sensing operation are different from each other during the second sensing operation.
    Type: Application
    Filed: December 8, 2017
    Publication date: November 8, 2018
    Inventors: Hee Joung PARK, Kyeong Seung KANG, Won Chul SHIN, Dong Hyuk CHAE
  • Publication number: 20180046574
    Abstract: At least one address scheduling method includes selecting a first bit line, selecting a first string connected to the first bit line, performing address scheduling on N pages of each of multi-level cells in the first string sequentially from a bottom word line to a top word line, and after completing the address scheduling on all word lines in the first string, performing address scheduling on second to k-th strings sequentially in the same manner as performed with respect to the first string, where “k” is 2 or a natural number greater than 2.
    Type: Application
    Filed: October 23, 2017
    Publication date: February 15, 2018
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Chi Weon YOON, Dong Hyuk CHAE, Sang-Wan NAM, Jung-Yun YUN
  • Patent number: 9798659
    Abstract: At least one address scheduling method includes selecting a first bit line, selecting a first string connected to the first bit line, performing address scheduling on N pages of each of multi-level cells in the first string sequentially from a bottom word line to a top word line, and after completing the address scheduling on all word lines in the first string, performing address scheduling on second to k-th strings sequentially in the same manner as performed with respect to the first string, where “k” is 2 or a natural number greater than 2.
    Type: Grant
    Filed: August 27, 2015
    Date of Patent: October 24, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chi Weon Yoon, Dong Hyuk Chae, Sang-Wan Nam, Jung-Yun Yun