Abstract: A thin film transistor array panel includes: a gate wiring layer disposed on a substrate; an oxide semiconductor layer disposed on the gate wiring layer; and a data wiring layer disposed on the oxide semiconductor layer, in which the data wiring layer includes a main wiring layer including copper and a capping layer disposed on the main wiring layer and including a copper alloy.

Abstract: An OLED display and a method of manufacturing the same are disclosed. In one aspect, the OLED display includes a substrate and a semiconductor layer formed over the substrate, wherein the semiconductor layer includes a channel and a contact region formed on opposing sides of the channel. The display also includes an insulating layer formed over the semiconductor layer and having a contact hole exposing the contact region, and an OLED formed over the insulating layer, wherein the OLED is electrically connected to the contact region through the contact hole, and wherein at least a portion of the contact hole is formed directly above the contact region.

Abstract: A thin film transistor, a thin film transistor array panel including the same, and a method of manufacturing the same are provided, wherein the thin film transistor includes a channel region including an oxide semiconductor, a source region and a drain region connected to the channel region and facing each other at both sides with respect to the channel region, an insulating layer positioned on the channel region, and a gate electrode positioned on the insulating layer, wherein an edge boundary of the gate electrode and an edge boundary of the channel region are substantially aligned.

Abstract: The present invention relates to a method for manufacturing a conductive metal thin film, including: preparing a conductive metal coating solution by adding carboxylic acid to a dispersion including a conductive metal particle having a core/shell structure; coating the conductive metal coating solution on a top portion of a substrate, heat-treating it, and removing an metal oxide layer of the surface of the conductive metal particle having the core/shell structure; and forming a thin film of the conductive metal particle from which the metal oxide layer is removed.

Abstract: A thin film transistor display panel includes: a gate electrode, a source electrode and a drain electrode which are included in a thin film transistor on a substrate; a data line connected to the source electrode; a pixel link member connecting the drain electrode to a pixel electrode; and a gate pad connected to the gate electrode through a gate line and including a first gate subpad, a second gate subpad and a gate pad link member, in which the pixel link member and the gate pad link member are substantially same in thickness.

Abstract: Provided is a thin film transistor array panel. The thin film transistor array panel according to exemplary embodiments of the present invention includes: a gate wiring layer disposed on a substrate; an oxide semiconductor layer disposed on the gate wiring layer; and a data wiring layer disposed on the oxide semiconductor layer, in which the data wiring layer includes a main wiring layer including copper and a capping layer disposed on the main wiring layer and including a copper alloy.

Abstract: A display substrate and a method for manufacturing a display substrate are disclosed. In the method, a gate electrode is formed on a base substrate. An active pattern is formed using an oxide semiconductor. The active pattern partially overlaps the gate electrode. A first insulation layer pattern and a second insulation layer pattern are sequentially formed on the active pattern. The first insulation layer pattern and the second insulation layer pattern overlap the gate electrode. A third insulation layer is formed to cover the active pattern, the first insulation layer pattern and the second insulation layer pattern. Either the first insulation layer pattern or the second insulation layer pattern includes aluminum oxide. Forming the first insulation layer pattern and the second insulation layer pattern includes performing a backside exposure process using the gate electrode as an exposure mask.

Abstract: A liquid crystal display includes a transparent insulation substrate, a first polarizer, and a semiconductor layer, a thin film transistor, and a backlight unit. The first polarizer is disposed on the transparent insulation substrate. The first polarizer includes a light blocking film and metal wires. The semiconductor layer, disposed on the light blocking film, has a perimeter aligned with a perimeter of the light blocking film. The thin film transistor, disposed on the semiconductor layer, includes a source region and a drain region disposed in the semiconductor layer. The backlight unit, disposed under the transparent insulation substrate, provides light to the transparent insulation substrate. The blocking film reflects substantially all of the light. Gaps are disposed between the metal wires.

Abstract: A thin film transistor array panel and a manufacturing method capable of forming an insulating layer made of different materials for a portion contacting an oxide semiconductor and a second portion without an additional process. Source and drain electrodes of the thin film transistor each include a lower layer and an upper layer. A first passivation layer contacts the lower layer of the source and drain electrodes but does not contact the upper layer of the source and drain electrodes, and a second passivation layer is disposed on the upper layer of the source and drain electrodes. The first passivation layer may be made of silicon oxide, and the second passivation may be made of silicon nitride.

Abstract: The present invention relates to a regulator having an electronic valve installed therein. The A regulator having an electronic valve installed therein, the regulator including: a first pressure reducing part connected to an inlet port; and a second pressure reducing part connected to the first pressure reducing part, wherein the second pressure reducing part includes: a pressure reducing chamber into which fuel is introduced from the first pressure reducing part; an orifice formed in the pressure reducing chamber; a valve shaft for opening and closing the orifice; a diaphragm for moving the valve shaft by use of an input pressure and an output pressure; and a spring for resiliently supporting the diaphragm, wherein an auxiliary conduit is formed to interconnect the pressure reducing chamber and an upper space of the diaphragm, and an electronic valve for controlling the pressure of an outlet port is installed on the auxiliary conduit.

Abstract: A three-dimensional map-generating apparatus and method using structured light. The apparatus for generating a three-dimensional map using structured light includes an odometer detecting the pose of a mobile robot, and a distance-measuring sensor including a light source module that emits light upward and a camera module that captures an image formed by light reflected from an obstacle, and measuring a distance to the obstacle using the captured image. The apparatus measures a distance to the obstacle using the distance-measuring sensor while changing the relative pose of the mobile robot, thereby generating a three-dimensional map.

Abstract: A thin film transistor, a thin film transistor array panel including the same, and a method of manufacturing the same are provided, wherein the thin film transistor includes a channel region including an oxide semiconductor, a source region and a drain region connected to the channel region and facing each other at both sides with respect to the channel region, an insulating layer positioned on the channel region, and a gate electrode positioned on the insulating layer, wherein an edge boundary of the gate electrode and an edge boundary of the channel region are substantially aligned.

Abstract: A thin film transistor according to an exemplary embodiment of the present invention includes an oxide semiconductor. A source electrode and a drain electrode face each other. The source electrode and the drain electrode are positioned at two opposite sides, respectively, of the oxide semiconductor. A low conductive region is positioned between the source electrode or the drain electrode and the oxide semiconductor. An insulating layer is positioned on the oxide semiconductor and the low conductive region. A gate electrode is positioned on the insulating layer. The insulating layer covers the oxide semiconductor and the low conductive region. A carrier concentration of the low conductive region is lower than a carrier concentration of the source electrode or the drain electrode.

Abstract: A thin film transistor, a thin film transistor array panel including the same, and a method of manufacturing the same are provided, wherein the thin film transistor includes a channel region including an oxide semiconductor, a source region and a drain region connected to the channel region and facing each other at both sides with respect to the channel region, an insulating layer positioned on the channel region, and a gate electrode positioned on the insulating layer, wherein an edge boundary of the gate electrode and an edge boundary of the channel region are substantially aligned.

Abstract: A thin film transistor includes a bottom gate electrode, a top gate electrode and an active pattern. The top gate electrode includes a transparent conductive material and overlaps with the bottom gate electrode. A boundary of the bottom gate electrode and a boundary of the top gate electrode are coincident with each other in a cross-sectional view. The active pattern includes a source portion, a drain portion and a channel portion disposed between the source portion and the drain portion. The channel portion overlaps with the bottom gate electrode and the top gate electrode.

Abstract: A thin film transistor includes: a substrate; an oxide semiconductor layer disposed on the substrate; a source electrode and a drain electrode each connected to the oxide semiconductor layer and facing each other with respect to the oxide semiconductor layer; an insulating layer disposed on the oxide semiconductor layer; and a gate electrode disposed on the insulating layer. The insulating layer includes a first layer that includes silicon oxide (SiOx), a second layer that is a hydrogen blocking layer, and a third layer that includes silicon nitride (SiNx). The first, second and third layers are sequentially stacked.

Abstract: A thin film transistor according to an exemplary embodiment of the present invention includes an oxide semiconductor. A source electrode and a drain electrode face each other. The source electrode and the drain electrode are positioned at two opposite sides, respectively, of the oxide semiconductor. A low conductive region is positioned between the source electrode or the drain electrode and the oxide semiconductor. An insulating layer is positioned on the oxide semiconductor and the low conductive region. A gate electrode is positioned on the insulating layer. The insulating layer covers the oxide semiconductor and the low conductive region. A carrier concentration of the low conductive region is lower than a carrier concentration of the source electrode or the drain electrode.

Abstract: A display substrate and a method for manufacturing a display substrate are disclosed. In the method, a gate electrode is formed on a base substrate. An active pattern is formed using an oxide semiconductor. The active pattern partially overlaps the gate electrode. A first insulation layer pattern and a second insulation layer pattern are sequentially formed on the active pattern. The first insulation layer pattern and the second insulation layer pattern overlap the gate electrode. A third insulation layer is formed to cover the active pattern, the first insulation layer pattern and the second insulation layer pattern. Either the first insulation layer pattern or the second insulation layer pattern includes aluminum oxide. Forming the first insulation layer pattern and the second insulation layer pattern includes performing a backside exposure process using the gate electrode as an exposure mask.

Abstract: A thin film transistor array panel and a manufacturing method capable of forming an insulating layer made of different materials for a portion contacting an oxide semiconductor and a second portion without an additional process. Source and drain electrodes of the thin film transistor each include a lower layer and an upper layer. A first passivation layer contacts the lower layer of the source and drain electrodes but does not contact the upper layer of the source and drain electrodes, and a second passivation layer is disposed on the upper layer of the source and drain electrodes. The first passivation layer may be made of silicon oxide, and the second passivation may be made of silicon nitride.

Abstract: A thin film transistor array panel and a manufacturing method capable of forming an insulating layer made of different materials for a portion contacting an oxide semiconductor and a second portion without an additional process. The thin film transistor array panel includes: a gate electrode; a source electrode and a drain electrode spaced apart from each other, each of the source and drain electrodes comprising a lower layer and an upper layer; an insulating layer disposed between the gate electrode and the source and drain electrodes; a semiconductor, the source electrode and the drain electrode being electrically connected to the semiconductor; a first passivation layer contacting the lower layer of the source and drain electrodes but not contacting the upper layer of the source and drain electrodes; and a second passivation layer disposed on the upper layer of the source and drain electrodes.