Abstract: A semiconductor memory unit includes first to Nth variable resistance elements each having different resistance values according to values stored therein, wherein N is a natural number equal to or greater than 2; a reference resistance element having a first reference resistance value; and first to Nth comparison units which correspond to the first to Nth variable resistance elements, respectively, and each of which determines whether a resistance value of the corresponding variable resistance element is greater or less than a second reference resistance value, wherein the first to Nth comparison units are commonly coupled to the reference resistance element.

Abstract: According to one embodiment, a resistance change memory includes the following configuration. A first inverter includes first input and first output terminals and first and second voltage terminals. A second inverter includes second input and second output terminals and third and fourth voltage terminals. The second input terminal is connected to the first output terminal. The second output terminal is connected to the first input terminal. First and second transistors are connected to the first and second output terminals, respectively. Third and fourth transistors are connected to the first and third voltage terminals, respectively. A fifth transistor is connected between the first voltage terminal and the first memory cell. A sixth transistor is connected to the third voltage terminal. A controller turns on the first and second transistors, after turning off the fifth and sixth transistors.

Abstract: An electronic device comprising a semiconductor memory unit that may include a plurality of data transfer lines; a plurality of columns including a plurality of memory cells; at least one redundancy column including a plurality of redundancy memory cells and configured to replace at least one column among the plurality of columns; a repair select information generation unit configured to store a column address of the at least one column to be replaced among the plurality of columns and generate a plurality of repair select information in response to the stored column address; and a plurality of repair selection units connected with data transfer lines corresponding to them among the plurality of data transfer lines, columns corresponding to them among the plurality of columns and the at least one redundancy column, and each configured to electrically connect a column selected among a column corresponding to it and the at least one redundancy column, to a data transfer line corresponding to it, in response to

Abstract: According to one embodiment, a resistance change memory includes a memory cell, a sense amplifier and a global bit line. The memory cell is disposed at a location where a local bit line and a word line intersect each other. The memory cell is connected to both the local bit line and the word line. The sense amplifier reads data stored on the memory cell by supplying a read current to the memory cell. The global bit line is connected between the local bit line and the sense amplifier. The global bit line feeds the read current supplied by the sense amplifier to the local bit line. The sense amplifier charges the global bit line, before the local bit line and the global bit line are connected to each other.

Abstract: A system-on-chip includes a clock controller configured to decrease an operating frequency of at least one function block based on a change in an operating state of the at least one function block from an active state to an idle state. In a method of operating a system-on-chip including at least one function block, an operating frequency of the at least one function block is decreased based on a change in an operating state of the at least one function block from an active state to an idle state. The decreased operating frequency is greater than zero.

Abstract: A scanning method used to scan documents in a scanning system, the system including a scanner and a user host computer having a technology without an interesting name (TWAIN) driver, the scanner and the user host computer connected by a local interface and a network, includes selecting one of the local interface or the network to connect the scanner and the user host computer; if the network is selected, connecting the TWAIN driver to the scanner via the selected network to control scanning processes of the scanner; and performing scanning according to the selected local interface or the network.

Abstract: Disclosed is a method of controlling a semiconductor memory device including a write driver. A method of controlling a phase change memory device includes turning on switches connected to a global bit line and a local bit line, respectively, enabling a write driver connected to the switches, enabling a word line, and enabling a memory cell to be accessed by the word line, wherein control is performed so that electric charges supplied from the write driver through the switches are charged when the write driver is enabled.

Abstract: In an electronic device including a semiconductor memory, the semiconductor memory may include a unit storage cell including a variable resistor having a resistance value that is changed according to current flowing through both terminals of the variable resistor and a selection element that is electrically coupled to one terminal of the variable resistor, a unit current generation section that generates the current flowing through both terminals by using predetermined voltage according to a polarity of current data as compared with existing data, and a pad that receives the predetermined voltage from an exterior and allows the current flowing through both terminals to be measured from an exterior.

Abstract: According to one embodiment, a resistance change memory includes a memory cell, a sense amplifier and a global bit line. The memory cell is disposed at a location where a local bit line and a word line intersect each other. The memory cell is connected to both the local bit line and the word line. The sense amplifier reads data stored on the memory cell by supplying a read current to the memory cell. The global bit line is connected between the local bit line and the sense amplifier. The global bit line feeds the read current supplied by the sense amplifier to the local bit line. The sense amplifier charges the global bit line, before the local bit line and the global bit line are connected to each other.

Abstract: A system-on-chip includes a clock controller configured to decrease an operating frequency of at least one function block based on a change in an operating state of the at least one function block from an active state to an idle state. In a method of operating a system-on-chip including at least one function block, an operating frequency of the at least one function block is decreased based on a change in an operating state of the at least one function block from an active state to an idle state. The decreased operating frequency is greater than zero.

Abstract: According to one embodiment, a resistance change memory includes a memory cell array, an address counter, a word line driver, a power supply circuit, and a write driver. Memory cells include resistive storage elements and cell transistors. The power supply circuit generates a stress voltage different from a power supply voltage used to write data into the memory cells in a normal operation. The write driver applies the stress voltage across first bit and source lines to pass a stress current through the memory cell selected by a first word line. The write driver applies the stress voltage across second bit and source lines to pass the stress current through the memory cell selected by a second word line.

Abstract: A semiconductor apparatus includes: a first bank group comprising a plurality of first banks; a second bank group comprising a plurality of second banks arranged adjacent to the first bank group; a write operation controller arranged between the first and second bank groups so as to be adjacent to the first and second bank groups, and configured to control write operations of the first and second bank groups; and a read operation controller arranged adjacent to any one of the first and second bank groups and configured to control read operations of the first and second bank groups.

Abstract: An intermediate shaft of a vehicle steering apparatus can prevent foreign matter, for example, moisture, dust or oil, from being introduced into the intermediate shaft even from a process of transporting the intermediate shaft to assemble it to a vehicle, and even when the intermediate shaft is assembled to the vehicle and the vehicle is driven. As a result, it is possible to prevent a component of the intermediate shaft from being deformed or damaged.

Abstract: According to one embodiment, a memory device includes a memory cell, a sense amplifier, unit structures and a reference signal generator. Each structure includes a first end, a first transistor, a first local line, a variable resistance element, a second transistor, a second local line, and a third transistor coupled in series. The reference signal generator includes first to fourth global lines, and first and second ones of the unit structures. The first unit structure is coupled at the first end to the first global line and coupled at the second end to the third global line. The second unit structure is coupled at the first end to the fourth global line and coupled at the second end to the second global line.

Abstract: A system-on-chip includes a clock controller configured to decrease an operating frequency of at least one function block based on a change in an operating state of the at least one function block from an active state to an idle state. In a method of operating a system-on-chip including at least one function block, an operating frequency of the at least one function block is decreased based on a change in an operating state of the at least one function block from an active state to an idle state. The decreased operating frequency is greater than zero.

Abstract: A phase change memory device includes: a memory cell arranged at a region where a word line and a bit line cross each other; and a control logic including: a program control logic configured to control a program operation of the memory cell; a read control logic configured to control a read operation of the memory cell; and an operation complete signal transfer unit configured to adjust a transfer time point of an operation complete signal transferred between the program control logic and the read control logic.

Abstract: A semiconductor device and a method for operating the same are provided relating to a nonvolatile memory device for sensing data using resistance change. The semiconductor device comprises a verification read control unit configured to sequentially output verification read data received from a sense amplifier into a global input/output line in response to a test signal, and a read data latch unit configured to store sequentially the verification read data received from the global input output line in response to a latch enable signal in activation of the test signal.

Abstract: The present invention relates to a semiconductor device, and more particularly, to a semiconductor memory device capable of supplying and measuring an electric current through a pad. The semiconductor device includes a memory cell, a data pad configured to receive data to be programmed into the memory cell or a write current to be supplied to the memory cell from an external device, and output data read out from the memory cell or a cell current flowing from the memory cell to the external device, and a path switching unit configured to set up a path so that the memory cell and the data pad are directly coupled when a test operation is performed.

Abstract: According to one embodiment, a resistance change memory includes a memory cell, a sense amplifier and a global bit line. The memory cell is disposed at a location where a local bit line and a word line intersect each other. The memory cell is connected to both the local bit line and the word line. The sense amplifier reads data stored on the memory cell by supplying a read current to the memory cell. The global bit line is connected between the local bit line and the sense amplifier. The global bit line feeds the read current supplied by the sense amplifier to the local bit line. The sense amplifier charges the global bit line, before the local bit line and the global bit line are connected to each other.

Abstract: According to one embodiment, a memory device includes a memory cell, a sense amplifier, unit structures and a reference signal generator. Each structure includes a first end, a first transistor, a first local line, a variable resistance element, a second transistor, a second local line, and a third transistor coupled in series. The reference signal generator includes first to fourth global lines, and first and second ones of the unit structures. The first unit structure is coupled at the first end to the first global line and coupled at the second end to the third global line. The second unit structure is coupled at the first end to the fourth global line and coupled at the second end to the second global line.