Patents by Inventor Dong-sik Park

Dong-sik Park has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240079630
    Abstract: The present disclosure relates to a secondary battery manufacturing system in which a packaging unit of a secondary battery manufacturing facility are configured to have multiple packaging units, and having a multipackaging unit such that a transfer box in which an electrode assembly is seated is transferred to each of the packaging units by a transfer unit, and including an electrode supply unit having a plurality of stacking devices supplying an electrode assembly in which a plurality of battery cells are stacked, a tab welding unit, at least one packaging unit, at least one temporary buffer, and a transfer unit.
    Type: Application
    Filed: September 1, 2023
    Publication date: March 7, 2024
    Inventors: Yong Uk SHIN, Sang Sik CHO, Dae Woon NAM, Dong Jin PARK, Jae Gyun CHOI, Chi Hong AN
  • Publication number: 20240074258
    Abstract: An electronic device includes a display device, which may be fabricated using a described method. The display device includes a glass substrate including a first surface, a second surface opposite the first surface, and a side surface between the first surface and the second surface, an outermost structure on the first surface of the glass substrate and located adjacent to an edge of one side of the glass substrate, and a display area including a plurality of light emitting areas on the first surface of the glass substrate and located farther from the edge of the one side of the glass substrate than the outermost structure is. A minimum distance from the side surface of the glass substrate to the outermost structure is equal to 130 ?m or less.
    Type: Application
    Filed: May 5, 2023
    Publication date: February 29, 2024
    Inventors: Wan Jung KIM, Dong Jo KIM, Sun Hwa KIM, Young Ji KIM, Chang Sik KIM, Kyung Ah NAM, Hyo Young MUN, Yong Seung PARK, Yi Seul UM, Dae Sang YUN, Kwan Hee LEE, So Young LEE, Young Hoon LEE, Young Seo CHOI, Sun Young KIM, Ji Won SOHN, Do Young LEE, Seung Hoon LEE
  • Patent number: 11915790
    Abstract: A memory system includes a memory device including an interface circuit and a semiconductor memory, and a controller to generate a command for controlling the memory device. The interface circuit receives the command from the controller; determines whether the command is for the semiconductor memory or the interface circuit; and when it is determined that the command is for the interface circuit, performs a blocking operation to block transfer of the command between the interface circuit and the semiconductor memory and performs an internal operation of the interface circuit. The internal operation includes a signal controlling operation, a training operation, a read operation, an on-die termination operation, a ZQ calibration operation, or a driving force control operation.
    Type: Grant
    Filed: May 26, 2022
    Date of Patent: February 27, 2024
    Assignee: SK hynix Inc.
    Inventors: Chang Kyun Park, Young Sik Koh, Seung Jin Park, Dong Hyun Lee
  • Publication number: 20240057323
    Abstract: The present disclosure provides a semiconductor memory device with improved element performance and reliability. The semiconductor memory device includes a substrate, a gate electrode extending in a first direction in the substrate, a plurality of buried contacts on the substrate, and a fence in a trench between adjacent ones of the buried contacts. The fence is on the gate electrode. The fence includes a spacer film on side walls of the trench and extending in a second direction intersecting the first direction, and a filling film in the trench and on the spacer film. An upper surface of the spacer film is lower than an upper surface of the filling film with respect to the substrate.
    Type: Application
    Filed: October 23, 2023
    Publication date: February 15, 2024
    Inventors: Hyeon Woo JANG, Soo Ho SHIN, Dong Sik PARK, Jong Min LEE, Ji Hoon CHANG
  • Patent number: 11832442
    Abstract: The present disclosure provides a semiconductor memory device with improved element performance and reliability. The semiconductor memory device comprises a substrate, a gate electrode extending in a first direction in the substrate, a plurality of buried contacts on the substrate, and a fence in a trench between adjacent ones of the buried contacts. The fence is on the gate electrode. The fence includes a spacer film on side walls of the trench and extending in a second direction intersecting the first direction, and a filling film in the trench and on the spacer film. An upper surface of the spacer film is lower than an upper surface of the filling film with respect to the substrate.
    Type: Grant
    Filed: October 4, 2021
    Date of Patent: November 28, 2023
    Inventors: Hyeon Woo Jang, Soo Ho Shin, Dong Sik Park, Jong Min Lee, Ji Hoon Chang
  • Publication number: 20230328951
    Abstract: A semiconductor device may include a substrate including a cell array region, a data storage structure provided on the cell array region of the substrate, the data storage structure including a bottom electrode, a top electrode on the bottom electrode, and a dielectric layer interposed between the bottom electrode and the top electrode, a blocking layer provided on a top surface of the top electrode, a lower interlayer insulating layer provided on the blocking layer, and a lower contact penetrating the lower interlayer insulating layer and electrically connected to the top electrode. At least a portion of a side surface of the lower contact may contact the blocking layer.
    Type: Application
    Filed: January 17, 2023
    Publication date: October 12, 2023
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: DONG-SIK PARK, SOOHO SHIN, CHEOLHO BAEK
  • Publication number: 20230189510
    Abstract: A semiconductor device includes a substrate having an active cell region and an interfacial region adjacent to each other in a first direction, bit lines on the active cell region of the substrate that are spaced apart from each other in a second direction that intersects the first direction, and bit-line pads on the interfacial region of the substrate that are spaced apart from each other in the second direction. Each of the bit lines includes a first bit line and a second bit line that extend in the first direction and are spaced apart from each other in the second direction, a connection part that connects a first end of the first bit line to a second end of the second bit line, and a coupling part that connects one of the bit-line pads to one of the first bit line, the second bit line, and the connection part.
    Type: Application
    Filed: June 30, 2022
    Publication date: June 15, 2023
    Inventors: Jihoon CHANG, Dong-Wan KIM, Dong-Sik PARK
  • Publication number: 20230189504
    Abstract: A semiconductor memory device includes a landing pad on a substrate, a lower electrode on and connected to the landing pad, a dielectric layer on and extending along a profile of the lower electrode, an upper electrode on the dielectric layer, and an upper plate electrode on the upper electrode, the upper plate electrode including a first sub-plate electrode and a second sub-plate electrode doped with boron, a first concentration of the boron in the first sub-plate electrode being greater than a second concentration of the boron in the second sub-plate electrode.
    Type: Application
    Filed: September 27, 2022
    Publication date: June 15, 2023
    Inventors: Keon Hee PARK, Soo Ho SHIN, Hyeon-Woo JANG, Dong-Sik PARK, Ga Eun LEE
  • Publication number: 20230146012
    Abstract: Disclosed are semiconductor memory devices and their fabrication methods. The semiconductor memory device comprises a semiconductor substrate that includes a cell array region and a peripheral region, a plurality of bottom electrodes on the semiconductor substrate on the cell array region, a dielectric layer that conformally covers sidewalls and top surfaces of the bottom electrodes, and a top electrode on the dielectric layer and between the bottom electrodes. The top electrode includes a first metal layer, a silicon-germanium layer, a second metal layer, and a silicon layer that are sequentially stacked. An amount of boron in the silicon-germanium layer is greater than an amount of boron in the silicon layer.
    Type: Application
    Filed: September 28, 2022
    Publication date: May 11, 2023
    Inventors: HYEON-WOO JANG, DONG-WAN KIM, Keonhee PARK, DONG-SIK PARK, SOOHO SHIN, JIHOON CHANG
  • Publication number: 20230039149
    Abstract: Disclosed are semiconductor devices and their fabrication methods. The semiconductor device comprises a substrate including a peripheral block and cell blocks each including a cell center region, a cell edge region, and a cell middle region, and bit lines extending on each cell block in a first direction. The bit lines include center bit lines, middle bit lines, and edge bit lines. The bit line has first and second lateral surfaces opposite to each other in a second direction. The first lateral surface straightly extends along the first direction on the cell center region, the cell middle region, and the cell edge region. The second lateral surface straightly extends along the first direction on the cell center region and the cell edge region, and the second lateral surface extends along a third direction, that intersects the first direction and the second direction, on the cell middle region.
    Type: Application
    Filed: May 18, 2022
    Publication date: February 9, 2023
    Inventors: Dong-Wan KIM, Keonhee PARK, Dong-Sik PARK, Joonsuk PARK, Jihoon CHANG, Hyeon-Woo JANG
  • Publication number: 20230041059
    Abstract: A semiconductor device may include a substrate including a cell region, a peripheral region, and a boundary region between the cell region and the peripheral region, bit lines provided on the cell region and extended in a first direction parallel to a top surface of the substrate, bit line capping patterns provided on the bit lines, and a boundary pattern provided on the boundary region. End portions of the bit lines may be in contact with a first interface of the boundary pattern, and the bit line capping patterns may include the same material as the boundary pattern.
    Type: Application
    Filed: July 5, 2022
    Publication date: February 9, 2023
    Inventors: DONG-WAN KIM, Keonhee PARK, DONG-SIK PARK, Joonsuk PARK, JIHOON CHANG, HYEON-WOO JANG
  • Publication number: 20230039205
    Abstract: Disclosed are semiconductor memory devices and their fabrication methods. The method comprises providing a substrate including a cell array region and a boundary region, forming a device isolation layer that defines active sections on an upper portion of the substrate on the cell array region, forming an intermediate layer on the substrate on the boundary region, forming on the substrate an electrode layer that covers the intermediate layer on the boundary region, forming a capping layer on the electrode layer, forming an additional capping pattern including providing a first step difference to the capping layer on the boundary region, and allowing the additional capping pattern, the capping layer, and the electrode layer to proceed an etching process to form bit lines that run across the active sections. During the etching process, the electrode layer is simultaneously exposed on the cell array region and the boundary region.
    Type: Application
    Filed: April 19, 2022
    Publication date: February 9, 2023
    Inventors: Hyeon-Woo Jang, Dong-Wan Kim, Keonhee Park, Dong-sik Park, Joonsuk Park, Jihoon Chang
  • Publication number: 20230045674
    Abstract: A semiconductor device may include a substrate including a cell region and a peripheral region, a gate stack on the peripheral region, an interlayer insulating layer on the gate stack, peripheral circuit interconnection lines on the interlayer insulating layer, and an interconnection insulating pattern between the peripheral circuit interconnection lines. The interconnection insulating pattern may include a pair of vertical portions spaced apart from each other in a first direction parallel to a top surface of the substrate and a connecting portion connecting the vertical portions to each other. Each of the vertical portions of the interconnection insulating pattern may have a first thickness at a same level as top surfaces of the peripheral circuit interconnection lines and a second thickness at a same level as bottom surfaces of the peripheral circuit interconnection lines. The first thickness may be substantially equal to the second thickness.
    Type: Application
    Filed: May 6, 2022
    Publication date: February 9, 2023
    Inventors: Hyeon-Woo Jang, Dong-Wan Kim, Keonhee Park, Dong-Sik Park, Joonsuk Park, Jihoon Chang
  • Patent number: 11469157
    Abstract: The semiconductor device includes a substrate including an integrated circuit and a contact that are electrically connected to each other, an insulation layer covering the substrate and including metal lines, and a through electrode electrically connected to the integrated circuit. The insulation layer includes an interlayer dielectric layer on the substrate and an intermetal dielectric layer on the interlayer dielectric layer. The metal lines include a first metal line in the interlayer dielectric layer and electrically connected to the contact, and a plurality of second metal lines in the intermetal dielectric layer and electrically connected to the first metal line and the through electrode. The through electrode includes a top surface higher than a top surface of the contact.
    Type: Grant
    Filed: January 19, 2021
    Date of Patent: October 11, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-Wan Kim, Jung-Hoon Han, Dong-Sik Park
  • Publication number: 20220271044
    Abstract: A semiconductor device comprises a substrate comprising a cell region; a cell region isolation film in the substrate and extending along an outer edge of the cell region; a bit-line structure on the substrate and in the cell region, wherein the bit-line structure has a distal end positioned on the cell region isolation film; a cell spacer on a vertical side surface of the distal end of the bit-line structure; an etching stopper film extending along a side surface of the cell spacer and a top face of the cell region isolation film; and an interlayer insulating film on the etching stopper film, and on the side surface of the cell spacer, wherein the interlayer insulating film includes silicon nitride.
    Type: Application
    Filed: November 1, 2021
    Publication date: August 25, 2022
    Inventors: Seok Hyun Kim, Young Sin Kim, Dong Sik Park, Jong Min Lee, Joon Yong Choe
  • Publication number: 20220262803
    Abstract: The present disclosure provides a semiconductor memory device with improved element performance and reliability. The semiconductor memory device comprises a substrate, a gate electrode extending in a first direction in the substrate, a plurality of buried contacts on the substrate, and a fence in a trench between adjacent ones of the buried contacts. The fence is on the gate electrode. The fence includes a spacer film on side walls of the trench and extending in a second direction intersecting the first direction, and a filling film in the trench and on the spacer film. An upper surface of the spacer film is lower than an upper surface of the filling film with respect to the substrate.
    Type: Application
    Filed: October 4, 2021
    Publication date: August 18, 2022
    Inventors: Hyeon Woo JANG, Soo Ho SHIN, Dong Sik PARK, Jong Min LEE, Ji Hoon CHANG
  • Publication number: 20220139927
    Abstract: The present disclosure provides a semiconductor memory device capable of improving reliability and performance. The semiconductor memory device comprises a substrate including a cell region and a peripheral region around the cell region, a cell region isolation film which defines the cell region, a bit line structure in the cell region, a first peripheral gate structure on the peripheral region of the substrate, the first peripheral gate structure comprising a first peripheral gate conduction film and a first peripheral capping film on the first peripheral gate conduction film, a peripheral interlayer insulating film around the first peripheral gate structure and an insertion interlayer insulating film on the peripheral interlayer insulating film and the first peripheral gate structure, and including a material different from the peripheral interlayer insulating film. An upper face of the peripheral interlayer insulating film is lower than an upper face of the first peripheral capping film.
    Type: Application
    Filed: July 9, 2021
    Publication date: May 5, 2022
    Inventors: Ji Hoon CHANG, Jung-Hoon HAN, Ji Seok HONG, Dong-Sik PARK
  • Patent number: 11180589
    Abstract: The present invention relates to a novel metallocene catalyst compound for the production of a polyolefin resin having a high molecular weight and a wide molecular weight distribution or a method of preparing the same, and more particularly to a metallocene catalyst compound using a ligand containing a Group 15 or 16 element having a bulky substituent or a method of preparing the same. The present invention provides a novel metallocene catalyst compound represented by Chemical Formula 1 below.
    Type: Grant
    Filed: February 26, 2020
    Date of Patent: November 23, 2021
    Assignee: DL Chemical CO., LTD.
    Inventors: Seung Tack Yu, Yong Kim, Dong Sik Park, Yong Jae Jun
  • Patent number: 11177264
    Abstract: Semiconductor devices are provided. A semiconductor device includes a substrate including a plurality of active regions that extend longitudinally in a direction and an isolation region that electrically isolates the plurality of active regions from each other. The semiconductor device includes a gate trench that extends across the plurality of active regions and the isolation region. The semiconductor device includes a gate structure that extends in the gate trench. The semiconductor device includes a gate dielectric layer that is between the gate trench and the gate structure, in each of the plurality of active regions. The gate structure has a first width in the direction in each of the plurality of active regions and has a second width in the direction in the isolation region that is different from the first width.
    Type: Grant
    Filed: September 10, 2019
    Date of Patent: November 16, 2021
    Inventors: Jae-hyeon Jeon, Se-keun Park, Dong-sik Park, Seok-ho Shin
  • Publication number: 20210143086
    Abstract: The semiconductor device includes a substrate including an integrated circuit and a contact that are electrically connected to each other, an insulation layer covering the substrate and including metal lines, and a through electrode electrically connected to the integrated circuit. The insulation layer includes an interlayer dielectric layer on the substrate and an intermetal dielectric layer on the interlayer dielectric layer. The metal lines include a first metal line in the interlayer dielectric layer and electrically connected to the contact, and a plurality of second metal lines in the intermetal dielectric layer and electrically connected to the first metal line and the through electrode. The through electrode includes a top surface higher than a top surface of the contact.
    Type: Application
    Filed: January 19, 2021
    Publication date: May 13, 2021
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Dong-Wan KIM, Jung-Hoon HAN, Dong-Sik PARK