Abstract: A semiconductor device comprises a substrate comprising a cell region; a cell region isolation film in the substrate and extending along an outer edge of the cell region; a bit-line structure on the substrate and in the cell region, wherein the bit-line structure has a distal end positioned on the cell region isolation film; a cell spacer on a vertical side surface of the distal end of the bit-line structure; an etching stopper film extending along a side surface of the cell spacer and a top face of the cell region isolation film; and an interlayer insulating film on the etching stopper film, and on the side surface of the cell spacer, wherein the interlayer insulating film includes silicon nitride.

Abstract: The present disclosure provides a semiconductor memory device with improved element performance and reliability. The semiconductor memory device comprises a substrate, a gate electrode extending in a first direction in the substrate, a plurality of buried contacts on the substrate, and a fence in a trench between adjacent ones of the buried contacts. The fence is on the gate electrode. The fence includes a spacer film on side walls of the trench and extending in a second direction intersecting the first direction, and a filling film in the trench and on the spacer film. An upper surface of the spacer film is lower than an upper surface of the filling film with respect to the substrate.

Abstract: The present disclosure provides a semiconductor memory device capable of improving reliability and performance. The semiconductor memory device comprises a substrate including a cell region and a peripheral region around the cell region, a cell region isolation film which defines the cell region, a bit line structure in the cell region, a first peripheral gate structure on the peripheral region of the substrate, the first peripheral gate structure comprising a first peripheral gate conduction film and a first peripheral capping film on the first peripheral gate conduction film, a peripheral interlayer insulating film around the first peripheral gate structure and an insertion interlayer insulating film on the peripheral interlayer insulating film and the first peripheral gate structure, and including a material different from the peripheral interlayer insulating film. An upper face of the peripheral interlayer insulating film is lower than an upper face of the first peripheral capping film.

Abstract: The present invention relates to a novel metallocene catalyst compound for the production of a polyolefin resin having a high molecular weight and a wide molecular weight distribution or a method of preparing the same, and more particularly to a metallocene catalyst compound using a ligand containing a Group 15 or 16 element having a bulky substituent or a method of preparing the same. The present invention provides a novel metallocene catalyst compound represented by Chemical Formula 1 below.

Abstract: Semiconductor devices are provided. A semiconductor device includes a substrate including a plurality of active regions that extend longitudinally in a direction and an isolation region that electrically isolates the plurality of active regions from each other. The semiconductor device includes a gate trench that extends across the plurality of active regions and the isolation region. The semiconductor device includes a gate structure that extends in the gate trench. The semiconductor device includes a gate dielectric layer that is between the gate trench and the gate structure, in each of the plurality of active regions. The gate structure has a first width in the direction in each of the plurality of active regions and has a second width in the direction in the isolation region that is different from the first width.

Abstract: The semiconductor device includes a substrate including an integrated circuit and a contact that are electrically connected to each other, an insulation layer covering the substrate and including metal lines, and a through electrode electrically connected to the integrated circuit. The insulation layer includes an interlayer dielectric layer on the substrate and an intermetal dielectric layer on the interlayer dielectric layer. The metal lines include a first metal line in the interlayer dielectric layer and electrically connected to the contact, and a plurality of second metal lines in the intermetal dielectric layer and electrically connected to the first metal line and the through electrode. The through electrode includes a top surface higher than a top surface of the contact.

Abstract: The semiconductor device includes a substrate including an integrated circuit and a contact that are electrically connected to each other, an insulation layer covering the substrate and including metal lines, and a through electrode electrically connected to the integrated circuit. The insulation layer includes an interlayer dielectric layer on the substrate and an intermetal dielectric layer on the interlayer dielectric layer. The metal lines include a first metal line in the interlayer dielectric layer and electrically connected to the contact, and a plurality of second metal lines in the intermetal dielectric layer and electrically connected to the first metal line and the through electrode. The through electrode includes a top surface higher than a top surface of the contact.

Abstract: Disclosed herein are a chromium compound represented by Formula 1a or 1c and a catalyst system including the same, exhibiting superior catalytic activity in an olefin trimerization reaction: [{CH3(CH2)3CH(CH2CH3)CO2}2Cr(OH)]??[Formula 1a] [{CH3(CH2)3CH(CH2CH3)CO2}2Cr(OH)]4.2H2O.

Abstract: Provided in one embodiment of the present invention is a photovoltaic the lighting system comprising: an MPPT circuit unit for controlling a battery charging voltage by calculating the maximum power point of electrical energy generated from a photovoltaic panel; a battery charging unit for charging and discharging, in a battery, the electrical energy controlled by the MPPT circuit unit; a lighting unit in which a plurality of LEDs are combined; a lighting driver for turning on or off the lighting unit by supplying power supplied from the battery; and an integrated control board including a microprocessor, which checks a residual quantity of the battery, overcharging of the battery, a discharge quantity, a discharge time, and a lighting state and brightness of the lighting unit through the MPPT circuit unit, the battery charging unit, and the lighting driver so as to diagnose an error and perform integrated control.

Abstract: Provided in one embodiment of the present invention is a photovoltaic the lighting system comprising: an MPPT circuit unit for controlling a battery charging voltage by calculating the maximum power point of electrical energy generated from a photovoltaic panel; a battery charging unit for charging and discharging, in a battery, the electrical energy controlled by the MPPT circuit unit; a lighting unit in which a plurality of LEDs are combined; a lighting driver for turning on or off the lighting unit by supplying power supplied from the battery; and an integrated control board including a microprocessor, which checks a residual quantity of the battery, overcharging of the battery, a discharge quantity, a discharge time, and a lighting state and brightness of the lighting unit through the MPPT circuit unit, the battery charging unit, and the lighting driver so as to diagnose an error and perform integrated control.

Abstract: The present invention relates to a novel metallocene catalyst compound for the production of a polyolefin resin having a high molecular weight and a wide molecular weight distribution or a method of preparing the same, and more particularly to a metallocene catalyst compound using a ligand containing a Group 15 or 16 element having a bulky substituent or a method of preparing the same. The present invention provides a novel metallocene catalyst compound represented by Chemical Formula 1 below.

Abstract: Semiconductor devices are provided. A semiconductor device includes a substrate including a plurality of active regions that extend longitudinally in a direction and an isolation region that electrically isolates the plurality of active regions from each other. The semiconductor device includes a gate trench that extends across the plurality of active regions and the isolation region. The semiconductor device includes a gate structure that extends in the gate trench. The semiconductor device includes a gate dielectric layer that is between the gate trench and the gate structure, in each of the plurality of active regions. The gate structure has a first width in the direction in each of the plurality of active regions and has a second width in the direction in the isolation region that is different from the first width.

Abstract: Disclosed herein are a chromium compound represented by Formula 1a or 1c and a catalyst system including the same, exhibiting superior catalytic activity in an olefin trimerization reaction: [{CH3(CH2)3CH(CH2CH3)CO2}2Cr(OH)]??[Formula 1a] [{CH3(CH2)3CH(CH2CH3)CO2}2Cr(OH)]4.2H2O.

Abstract: Disclosed herein are a chromium compound represented by Formula 1a or 1b and a catalyst system including the same, exhibiting superior catalytic activity in an olefin trimerization reaction: [{CH3(CH2)3CH(CH2CH3)CO2}2Cr(OH)]??[Formula 1a] [{CH3CH2CH(CH2CH3)CO2}2Cr(OH)].

Abstract: The semiconductor device includes a substrate including an integrated circuit and a contact that are electrically connected to each other, an insulation layer covering the substrate and including metal lines, and a through electrode electrically connected to the integrated circuit. The insulation layer includes an interlayer dielectric layer on the substrate and an intermetal dielectric layer on the interlayer dielectric layer. The metal lines include a first metal line in the interlayer dielectric layer and electrically connected to the contact, and a plurality of second metal lines in the intermetal dielectric layer and electrically connected to the first metal line and the through electrode. The through electrode includes a top surface higher than a top surface of the contact.

Abstract: The semiconductor device includes a substrate including an integrated circuit and a contact that are electrically connected to each other, an insulation layer covering the substrate and including metal lines, and a through electrode electrically connected to the integrated circuit. The insulation layer includes an interlayer dielectric layer on the substrate and an intermetal dielectric layer on the interlayer dielectric layer. The metal lines include a first metal line in the interlayer dielectric layer and electrically connected to the contact, and a plurality of second metal lines in the intermetal dielectric layer and electrically connected to the first metal line and the through electrode. The through electrode includes a top surface higher than a top surface of the contact.

Abstract: A circuit board comprises a mother substrate including first and second scribing regions, the first scribing region extending in first direction, the second scribing region extending in second direction, the first and second directions crossing each other, the mother substrate including chip regions defined by the first and second scribing regions, and a through via penetrating the chip regions of the mother substrate. The mother substrate comprises a first alignment pattern protruding from a top surface of the mother substrate. The first alignment pattern is disposed on at least one of the scribing regions.

Abstract: The present invention relates to a novel bicyclic heteroaryl derivative, a pharmaceutically acceptable salt thereof, a hydrate thereof, and a solvate thereof having an improved inhibitory activity for protein kinases, and a pharmaceutical composition for preventing or treating an abnormal cell growth disorder comprising same as an active ingredient.

Abstract: A semiconductor chip is provided including an integrated circuit on a substrate; pads electrically connected to the integrated circuit; a lower insulating structure defining contact holes exposing the pads, respectively; and first, second and third conductive patterns electrically connected to the pads. The second conductive pattern is between the first conductive pattern and the third conductive pattern when viewed from a plan view. Each of the first to third conductive patterns includes a contact portion filling the contact hole, a first conductive line portion extending in one direction on the lower insulating structure, and a bonding pad portion. Ends of the bonding pad portions of the first and third conductive patterns protrude in the one direction as compared with an end of the bonding pad portion of the second conductive pattern when viewed from a plan view.

Abstract: A semiconductor device includes a substrate; a hydrogen insulating layer disposed on the substrate and including hydrogen ions; a first level layer disposed on the substrate and including a first wire and a second wire; a second level layer disposed on the substrate at a different level from the first level layer and including a third wire; an interlayer insulating layer disposed between the first level layer and the second level layer; a diffusion prevention layer contacting the third wire; a contact plug penetrating the interlayer insulating layer and electrically connecting the second wire to the third wire; and a dummy contact plug penetrating the interlayer insulating layer. The dummy contact plug contacts the first and second level layers, is spaced apart from the diffusion prevention layer, and is configured to provide a movement path for the hydrogen ions in the hydrogen insulating layer.