Patents by Inventor Dong-Soo Kim

Dong-Soo Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11791390
    Abstract: Disclosed is a semiconductor device for improving a gate induced drain leakage and a method for fabricating the same, and the method may include forming a trench in a substrate, lining a surface of the trench with an initial gate dielectric layer, forming a gate electrode to partially fill the lined trench, forming a sacrificial material spaced apart from a top surface of the gate electrode and to selectively cover a top corner of the lined trench, removing a part of the initial gate dielectric layer of the lined trench which is exposed by the sacrificial material in order to form an air gap, and forming a capping layer to cap a side surface of the air gap, over the gate electrode.
    Type: Grant
    Filed: November 18, 2021
    Date of Patent: October 17, 2023
    Assignee: SK hynix Inc.
    Inventors: Se-Han Kwon, Dong-Soo Kim
  • Publication number: 20230292494
    Abstract: A semiconductor device includes: a trench formed in a substrate; a gate dielectric layer covering sidewalls and a bottom surface of the trench; a first gate electrode gap-filling a bottom portion of the trench over the gate dielectric layer; a second gate electrode including a metal nitride which is the same as the first gate electrode over the first gate electrode and doped with a low work function adjusting element; a buffer layer covering a top surface of the second gate electrode and the gate dielectric layer exposed over second gate electrode; and a capping layer gap-filling the other portion of the trench over the buffer layer.
    Type: Application
    Filed: September 7, 2022
    Publication date: September 14, 2023
    Inventors: Dong Soo KIM, Se Han KWON
  • Publication number: 20230292495
    Abstract: An embodiment of the present invention provides a semiconductor device capable of improving gate induced drain leakage and a method for fabricating the same, According to an embodiment of the present invention, a semiconductor device comprises a substrate including a trench; a gate insulating layer covering a bottom surface and a sidewall of the trench; and a gate electrode structure and a capping layer sequentially stacked on the gate insulating layer and filling the trench, wherein the gate electrode structure includes: a first gate electrode including a metal nitride; a second gate electrode formed over the first gate electrode, having the same metal nitride as the first gate electrode, and having a lower work function than that of the first gate electrode; and a third gate electrode formed over the second gate electrode, having a thickness smaller than that of the second gate electrode, and including a non-metal material.
    Type: Application
    Filed: September 19, 2022
    Publication date: September 14, 2023
    Inventors: Dong Soo KIM, Tae Kyun Kim
  • Publication number: 20230290848
    Abstract: A semiconductor device includes: a substrate including a gate trench; a gate dielectric layer formed along sidewalls and bottom surfaces of the gate trench; a high work function layer and a lower gate electrode that fill a bottom portion of the gate trench over the gate dielectric layer; an upper gate electrode including a low work function adjusting element over the lower gate electrode and including the same metal nitride as a material of the lower gate electrode; and a capping layer that gap-fills the other portion of the gate trench over the upper gate electrode.
    Type: Application
    Filed: November 3, 2022
    Publication date: September 14, 2023
    Inventors: Dong Soo KIM, Se Han KWON
  • Publication number: 20230282518
    Abstract: A method for fabricating a semiconductor device includes forming a trench in a substrate, forming a gate dielectric layer on a surface of the trench, forming a lower gate, which partially fills the trench, over the gate dielectric layer, forming a low work function layer over the lower gate, forming a spacer over the low work function layer, etching the low work function layer to be self-aligned with the spacer in order to form vertical gate on both upper edges of the lower gate, and forming an upper gate over the lower gate between inner sidewalls of the vertical gate.
    Type: Application
    Filed: May 12, 2023
    Publication date: September 7, 2023
    Inventors: Dong-Soo KIM, Se-Han KWON
  • Patent number: 11744124
    Abstract: A display device includes signal lines and pixels connected thereto. A first pixel includes a first transistor including a first gate electrode, a first channel region overlapping the first gate electrode, a first source region, and a second drain region facing the first source region, with the first channel region interposed between the first source region and the second drain region. A third transistor includes a third gate electrode, a third channel region overlapping the third gate electrode, a third drain region connected to the first gate electrode, and a third source region facing the third drain region with the third channel region interposed between the third source region and the third drain region. A shielding part overlaps a boundary between the third source region and the third channel region and does not overlap a boundary between the third drain region and the third channel region.
    Type: Grant
    Filed: August 8, 2022
    Date of Patent: August 29, 2023
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Jun Won Choi, Dong Soo Kim, Hyun-Chol Bang, Chang Soo Pyon, Ji-Eun Lee
  • Patent number: 11720191
    Abstract: A display device includes: a first substrate including a display area and a non-display area; a second substrate facing the first substrate; a sealing member disposed in the non-display area and coupling the first substrate to the second substrate; a sensing contact area disposed at an inner side of the sealing member; a sensing signal line disposed in the sensing contact area; a sensing contact pattern disposed in the sensing contact area and electrically connected to the sensing signal line; a control signal line disposed between the first substrate and the sensing signal line; and a shielding pattern disposed between the control signal line and the sensing signal line, the shielding pattern overlapping the control signal line or the sensing signal line.
    Type: Grant
    Filed: January 13, 2021
    Date of Patent: August 8, 2023
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Yong Jun Jo, Kwang Chui Jung, Dong Soo Kim, Mi Na Kim
  • Publication number: 20230241637
    Abstract: Provided is a pattern forming apparatus which may form a pattern on a substrate with high precision by using a material including an organic material, the pattern forming apparatus including: a capillary facing a grounded substrate and capable of storing a solution including a sample; a power source applying a voltage to the capillary; a stencil mask disposed between the capillary and the substrate, and including an opening through which the sample passes; and a cross-direction actuator moving the stencil mask in a cross direction crossing a direction in which the sample passes.
    Type: Application
    Filed: January 25, 2023
    Publication date: August 3, 2023
    Inventors: Joon-wan Kim, Dong Soo Kim, Min Hun Jung, Hyun Ah Lee
  • Patent number: 11712600
    Abstract: The present invention is directed to a multiply convertible bicycle exercise apparatus, and intends to provide a multiply convertible bicycle exercise apparatus that allows the form of a bicycle exercise apparatus to be freely converted into various forms such as standing, sitting, dancing, and riding forms, so that various types of exercise can be enjoyed, various types of exercise apparatuses can be replaced with a single exercise apparatus, and the shape and size of the exercise apparatus can be adjusted to fit the physical size of a user even in a converted state, and that changes the location of the center of gravity of the bicycle exercise apparatus from the existing lower portion to the upper portion where a user's groin is located, so that the bicycle exercise apparatus is stable in connection with the center of gravity and is superior in terms of stability.
    Type: Grant
    Filed: January 13, 2021
    Date of Patent: August 1, 2023
    Inventor: Dong Soo Kim
  • Patent number: 11694930
    Abstract: A method for fabricating a semiconductor device includes forming a trench in a substrate, forming a gate dielectric layer on a surface of the trench, forming a lower gate, which partially fills the trench, over the gate dielectric layer, forming a low work function layer over the lower gate, forming a spacer over the low work function layer, etching the low work function layer to be self-aligned with the spacer in order to form vertical gate on both upper edges of the lower gate, and forming an upper gate over the lower gate between inner sidewalls of the vertical gate.
    Type: Grant
    Filed: December 23, 2021
    Date of Patent: July 4, 2023
    Assignee: SK hynix Inc.
    Inventors: Dong-Soo Kim, Se-Han Kwon
  • Patent number: 11600710
    Abstract: Disclosed is a semiconductor device for improving a gate induced drain leakage and a method for fabricating the same, and the semiconductor device includes a substrate, a first doped region and a second doped region formed to be spaced apart from each other by a trench in the substrate, a first gate dielectric layer over the trench, a lower gate over the first gate dielectric layer, an upper gate over the lower gate and having a smaller width than the lower gate, and a second gate dielectric layer between the upper gate and the first gate dielectric layer.
    Type: Grant
    Filed: July 1, 2021
    Date of Patent: March 7, 2023
    Assignee: SK hynix Inc.
    Inventor: Dong-Soo Kim
  • Patent number: 11590445
    Abstract: Provided is an apparatus for treating waste gas of the electronics industry, and the apparatus includes: a reaction chamber in which an inlet and an outlet are formed and an inner space for purifying waste gas is formed; a first partition plate extending from an inner wall of the reaction chamber facing the inlet in a direction toward the inlet, dividing the inner space into a pre-treatment zone for collecting dust in the waste gas and a remaining purification zone; a second partition plate extending vertically downward from a ceiling of the reaction chamber, dividing the purification zone into a thermal decomposition zone for heating and thermally decomposing waste gas and a post-treatment zone; and a heater installed at the ceiling of the reaction chamber so as to be located in the thermal decomposition zone to thermally decompose a perfluorinated compound by heating waste gas introduced into the thermal decomposition zone; and a dry scrubber unit including one or more catalysts to collect at least one of t
    Type: Grant
    Filed: July 8, 2021
    Date of Patent: February 28, 2023
    Inventors: Dong Soo Kim, Chul Hwan Kim, Hyun Kyung Kim
  • Publication number: 20230038881
    Abstract: Present invention relates to a semiconductor device including a buried gate structure. A semiconductor device comprises a substrate; a first fluorine-containing layer over the substrate; a trench formed in the first fluorine-containing layer and extended into the substrate; a gate dielectric layer formed over the trench; a gate electrode formed over the gate dielectric layer and filling a portion of the trench; a second fluorine-containing layer formed over the gate electrode; and a fluorine-containing passivation layer between the gate dielectric layer and the gate electrode.
    Type: Application
    Filed: March 8, 2022
    Publication date: February 9, 2023
    Inventors: Dong Soo KIM, Tae Kyun KIM
  • Publication number: 20220399456
    Abstract: The present invention relates to a semiconductor device with improved reliability and a method for manufacturing the same. A semiconductor device according to the present invention may comprise: a substrate including a gate trench; a gate insulating layer formed on a surface of the gate trench; and silicon-doped metal nitride on the gate insulating layer, wherein the silicon-doped metal nitride has a silicon concentration of less than 1 at %.
    Type: Application
    Filed: January 31, 2022
    Publication date: December 15, 2022
    Inventors: Dong Soo KIM, Jung Ho SEO
  • Publication number: 20220387922
    Abstract: Provided is an apparatus for treating waste gas of the electronics industry, and the apparatus includes: a reaction chamber in which an inlet and an outlet are formed and an inner space for purifying waste gas is formed; a first partition plate extending from an inner wall of the reaction chamber facing the inlet in a direction toward the inlet, dividing the inner space into a pre-treatment zone for collecting dust in the waste gas and a remaining purification zone; a second partition plate extending vertically downward from a ceiling of the reaction chamber, dividing the purification zone into a thermal decomposition zone for heating and thermally decomposing waste gas and a post-treatment zone; and a heater installed at the ceiling of the reaction chamber so as to be located in the thermal decomposition zone to thermally decompose a perfluorinated compound by heating waste gas introduced into the thermal decomposition zone; and a dry scrubber unit including one or more catalysts to collect at least one of t
    Type: Application
    Filed: July 8, 2021
    Publication date: December 8, 2022
    Inventors: Dong Soo Kim, Chul Hwan Kim, Hyun Kyung Kim
  • Publication number: 20220376018
    Abstract: A display device includes signal lines and pixels connected thereto. A first pixel includes a first transistor including a first gate electrode, a first channel region overlapping the first gate electrode, a first source region, and a second drain region facing the first source region, with the first channel region interposed between the first source region and the second drain region. A third transistor includes a third gate electrode, a third channel region overlapping the third gate electrode, a third drain region connected to the first gate electrode, and a third source region facing the third drain region with the third channel region interposed between the third source region and the third drain region. A shielding part overlaps a boundary between the third source region and the third channel region and does not overlap a boundary between the third drain region and the third channel region.
    Type: Application
    Filed: August 8, 2022
    Publication date: November 24, 2022
    Inventors: Jun Won CHOI, Dong Soo Kim, Hyun-Choi Bang, Chang Soo Pyon, Ji-Eun Lee
  • Patent number: 11499074
    Abstract: Disclosed is an eco-friendly adhesive coating agent composition having high adhesion properties and fast-curing properties by using a thiol-modified epoxy intermediate. The composition includes: a main material including 25 to 40 parts by weight of polyoxypropyleneamine, 20 to 30 parts by weight of a cross-linking agent, 10 to 30 parts by weight of the thiol-modified epoxy intermediate, 10 to 20 parts by weight of an inorganic filler, 5 to 10 parts by weight of a pigment, and 2 to 5 parts by weight of an additive; and a curing agent including 60 to 80 parts by weight of a rubber-modified epoxy resin, 20 to 40 parts by weight of a polyol, 10 to 30 parts by weight of the thiol-modified epoxy intermediate, and 4 to 10 parts by weight of an additive, with respect to 100 parts by weight of an isocyanate mixture.
    Type: Grant
    Filed: May 29, 2020
    Date of Patent: November 15, 2022
    Inventors: Tae Yoon Seol, Dong Soo Kim, Dong Won Lee
  • Patent number: 11482163
    Abstract: A display device includes scan lines disposed in a first direction; data lines disposed in a second direction substantially perpendicular to the first direction; and unit pixel regions adjacent to the scan lines and the data lines, each unit pixel region including sub-pixels. A portion of an opening region of at least one of the sub-pixels overlaps a unit pixel region adjacent to a unit pixel region corresponding to the at least one of the sub-pixels, and a side of the opening region of the at least one of the sub-pixels extends in a third direction inclined with respect to each of the first direction and the second direction.
    Type: Grant
    Filed: August 23, 2021
    Date of Patent: October 25, 2022
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Jin Koo Chung, Dong Soo Kim, Taek Ju Jung, Seong Min Kim, Kyung Soo Jang, Kwang Chul Jung, Kyung Hyun Choi
  • Publication number: 20220314063
    Abstract: The present invention is directed to a multiply convertible bicycle exercise apparatus, and intends to provide a multiply convertible bicycle exercise apparatus that allows the form of a bicycle exercise apparatus to be freely converted into various forms such as standing, sitting, dancing, and riding forms, so that various types of exercise can be enjoyed, various types of exercise apparatuses can be replaced with a single exercise apparatus, and the shape and size of the exercise apparatus can be adjusted to fit the physical size of a user even in a converted state, and that changes the location of the center of gravity of the bicycle exercise apparatus from the existing lower portion to the upper portion where a user's groin is located, so that the bicycle exercise apparatus is stable in connection with the center of gravity and is superior in terms of stability.
    Type: Application
    Filed: January 13, 2021
    Publication date: October 6, 2022
    Inventor: Dong Soo KIM
  • Publication number: 20220320102
    Abstract: A semiconductor device includes: a gate trench formed into a semiconductor substrate; a gate dielectric layer formed in the gate trench to cover an inside surface of the gate trench; and a gate electrode disposed over the gate dielectric layer to fill the gate trench, wherein the gate electrode includes: second crystal grains formed in the gate trench; and first crystal grains disposed between the second crystal grains and the gate dielectric layer and having a smaller crystal grain size than the second crystal grains.
    Type: Application
    Filed: June 20, 2022
    Publication date: October 6, 2022
    Inventor: Dong-Soo KIM