Patents by Inventor Dong-Sun Sheen

Dong-Sun Sheen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10559589
    Abstract: Provided herein may be a semiconductor device and a method of manufacturing the same. The semiconductor device may include a memory string including memory cells coupled to each other in series via a channel layer, the memory string coupled between a bit line and a second source line. The semiconductor device may include a first source line electrically coupled to the second source line through the channel layer.
    Type: Grant
    Filed: May 7, 2018
    Date of Patent: February 11, 2020
    Assignee: SK hynix Inc.
    Inventors: In Su Park, Dong Sun Sheen
  • Patent number: 10546877
    Abstract: Provided herein may be a semiconductor device and a method of manufacturing the same. The semiconductor device may include a memory string including memory cells coupled to each other in series via a channel layer, the memory string coupled between a bit line and a second source line. The semiconductor device may include a first source line electrically coupled to the second source line through the channel layer.
    Type: Grant
    Filed: August 28, 2019
    Date of Patent: January 28, 2020
    Assignee: SK hynix Inc.
    Inventors: In Su Park, Dong Sun Sheen
  • Publication number: 20190386023
    Abstract: Provided herein may be a semiconductor device and a method of manufacturing the same. The semiconductor device may include a memory string including memory cells coupled to each other in series via a channel layer, the memory string coupled between a bit line and a second source line. The semiconductor device may include a first source line electrically coupled to the second source line through the channel layer.
    Type: Application
    Filed: August 28, 2019
    Publication date: December 19, 2019
    Applicant: SK hynix Inc.
    Inventors: In Su PARK, Dong Sun SHEEN
  • Publication number: 20190319045
    Abstract: The method of manufacturing a semiconductor device include: forming conductive patterns in interlayer spaces between interlayer insulating layers, the conductive patterns being separated from each other by a slit passing through the interlayer insulating layers, wherein the conductive patterns include a first by-product; generating a second by-product of a gas phase by reacting the first by-product remaining in the conductive patterns with source gas; and performing an out-gassing process to remove the second by-product.
    Type: Application
    Filed: June 25, 2019
    Publication date: October 17, 2019
    Inventors: Won Joon CHOI, Min Sung KO, Kyeong Bae KIM, Jong Gi KIM, Dong Sun SHEEN, Jung Myoung SHIM, Young Ho YANG, Hyeng Woo EOM, Kwang Wook LEE, Woo Jae CHUNG
  • Patent number: 10438969
    Abstract: Provided herein may be a semiconductor device and a method of manufacturing the same. The semiconductor device may include a memory string including memory cells coupled to each other in series via a channel layer, the memory string coupled between a bit line and a second source line. The semiconductor device may include a first source line electrically coupled to the second source line through the channel layer.
    Type: Grant
    Filed: May 7, 2018
    Date of Patent: October 8, 2019
    Assignee: SK hynix Inc.
    Inventors: In Su Park, Dong Sun Sheen
  • Patent number: 10373973
    Abstract: The method of manufacturing a semiconductor device include: forming conductive patterns in interlayer spaces between interlayer insulating layers, the conductive patterns being separated from each other by a slit passing through the interlayer insulating layers, wherein the conductive patterns include a first by-product; generating a second by-product of a gas phase by reacting the first by-product remaining in the conductive patterns with source gas; and performing an out-gassing process to remove the second by-product.
    Type: Grant
    Filed: April 24, 2018
    Date of Patent: August 6, 2019
    Assignee: SK hynix Inc.
    Inventors: Won Joon Choi, Min Sung Ko, Kyeong Bae Kim, Jong Gi Kim, Dong Sun Sheen, Jung Myoung Shim, Young Ho Yang, Hyeng Woo Eom, Kwang Wook Lee, Woo Jae Chung
  • Publication number: 20190096905
    Abstract: Provided herein may be a semiconductor device and a method of manufacturing the same. The semiconductor device may include a memory string including memory cells coupled to each other in series via a channel layer, the memory string coupled between a bit line and a second source line. The semiconductor device may include a first source line electrically coupled to the second source line through the channel layer.
    Type: Application
    Filed: May 7, 2018
    Publication date: March 28, 2019
    Applicant: SK hynix Inc.
    Inventors: In Su PARK, Dong Sun SHEEN
  • Publication number: 20190081066
    Abstract: The method of manufacturing a semiconductor device include: forming conductive patterns in interlayer spaces between interlayer insulating layers, the conductive patterns being separated from each other by a slit passing through the interlayer insulating layers, wherein the conductive patterns include a first by-product; generating a second by-product of a gas phase by reacting the first by-product remaining in the conductive patterns with source gas; and performing an out-gassing process to remove the second by-product.
    Type: Application
    Filed: April 24, 2018
    Publication date: March 14, 2019
    Inventors: Won Joon CHOI, Min Sung KO, Kyeong Bae KIM, Jong Gi KIM, Dong Sun SHEEN, Jung Myoung SHIM, Young Ho YANG, Hyeng Woo EOM, Kwang Wook LEE, Woo Jae CHUNG
  • Patent number: 9466609
    Abstract: The device includes plural control gates stacked on a substrate, plural first channels, configured to penetrate the control gates, and plural memory layer patterns, each located between the control gate and the first channel, configured to respectively surround the first channel, wherein the memory layer patterns are isolated from one another.
    Type: Grant
    Filed: November 13, 2014
    Date of Patent: October 11, 2016
    Assignee: SK Hynix Inc.
    Inventors: Min Soo Kim, Dong Sun Sheen, Young Jin Lee, Jin Hae Choi, Joo Hee Han, Sung Jin Whang
  • Patent number: 9385135
    Abstract: A nonvolatile memory device includes a substrate; a channel layer projecting from a surface of the substrate, in a direction perpendicular to the surface; a tunnel dielectric layer surrounding the channel layer; a plurality of interlayer dielectric layers and a plurality of control gate electrodes alternately formed along the channel layer; floating gate electrodes interposed between the tunnel dielectric layer and the plurality of control gate electrodes, the floating gate electrodes comprising a metal-semiconductor compound; and a charge blocking layer interposed between each of the plurality of control gate electrodes and each of the plurality of floating gate electrodes.
    Type: Grant
    Filed: December 16, 2014
    Date of Patent: July 5, 2016
    Assignee: SK Hynix Inc.
    Inventors: Sung-Jin Whang, Dong-Sun Sheen, Seung-Ho Pyi, Min-Soo Kim
  • Patent number: 9245962
    Abstract: A method of manufacturing a semiconductor device includes forming a sacrificial pattern, forming a first stacked structure including first material layers and second material layers alternately stacked on the sacrificial pattern, forming first semiconductor patterns passing through the first stacked structure and dielectric multi-layers surrounding the first semiconductor patterns, forming a slit passing through the first stacked structure and exposing the sacrificial pattern, forming a spacer on an inner wall of the slit, forming a first opening by removing the sacrificial pattern through the slit, forming a second opening by partially removing the dielectric multi-layers through the first opening to expose lower portions of the first semiconductor patterns, and forming a connection pattern in contact with the first semiconductor patterns in the first and second openings.
    Type: Grant
    Filed: January 20, 2015
    Date of Patent: January 26, 2016
    Assignee: SK Hynix Inc.
    Inventors: Ki Hong Yang, Dong Sun Sheen
  • Patent number: 9159570
    Abstract: A non-volatile memory device includes a channel layer vertically extending from a substrate, a plurality of inter-layer dielectric layers and a plurality of gate electrodes that are alternately stacked along the channel layer, and an air gap interposed between the channel layer and each of the plurality of gate electrodes. The non-volatile memory device may improve erase operation characteristics by suppressing back tunneling of electrons by substituting a charge blocking layer interposed between a gate electrode and a charge storage layer with an air gap, and a method for fabricating the non-volatile memory device.
    Type: Grant
    Filed: December 12, 2014
    Date of Patent: October 13, 2015
    Assignee: SK Hynix Inc.
    Inventors: Min-Soo Kim, Dong-Sun Sheen, Seung-Ho Pyi, Sung-Jin Whang
  • Publication number: 20150099339
    Abstract: A non-volatile memory device includes a channel layer vertically extending from a substrate, a plurality of inter-layer dielectric layers and a plurality of gate electrodes that are alternately stacked along the channel layer, and an air gap interposed between the channel layer and each of the plurality of gate electrodes. The non-volatile memory device may improve erase operation characteristics by suppressing back tunneling of electrons by substituting a charge blocking layer interposed between a gate electrode and a charge storage layer with an air gap, and a method for fabricating the non-volatile memory device.
    Type: Application
    Filed: December 12, 2014
    Publication date: April 9, 2015
    Inventors: Min-Soo KIM, Dong-Sun SHEEN, Seung-Ho PYI, Sung-Jin WHANG
  • Publication number: 20150099337
    Abstract: A nonvolatile memory device includes a substrate; a channel layer projecting from a surface of the substrate, in a direction perpendicular to the surface; a tunnel dielectric layer surrounding the channel layer; a plurality of interlayer dielectric layers and a plurality of control gate electrodes alternately formed along the channel layer; floating gate electrodes interposed between the tunnel dielectric layer and the plurality of control gate electrodes, the floating gate electrodes comprising a metal-semiconductor compound; and a charge blocking layer interposed between each of the plurality of control gate electrodes and each of the plurality of floating gate electrodes.
    Type: Application
    Filed: December 16, 2014
    Publication date: April 9, 2015
    Inventors: Sung-Jin WHANG, Dong-Sun SHEEN, Seung-Ho PYI, Min-Soo KIM
  • Publication number: 20150072491
    Abstract: The device includes plural control gates stacked on a substrate, plural first channels, configured to penetrate the control gates, and plural memory layer patterns, each located between the control gate and the first channel, configured to respectively surround the first channel, wherein the memory layer patterns are isolated from one another.
    Type: Application
    Filed: November 13, 2014
    Publication date: March 12, 2015
    Inventors: Min Soo KIM, Dong Sun SHEEN, Young Jin LEE, Jin Hae CHOI, Joo Hee HAN, Sung Jin WHANG
  • Patent number: 8928059
    Abstract: A nonvolatile memory device includes a substrate; a channel layer projecting from a surface of the substrate, in a direction perpendicular to the surface; a tunnel dielectric layer surrounding the channel layer; a plurality of interlayer dielectric layers and a plurality of control gate electrodes alternately formed along the channel layer; floating gate electrodes interposed between the tunnel dielectric layer and the plurality of control gate electrodes, the floating gate electrodes comprising a metal-semiconductor compound; and a charge blocking layer interposed between each of the plurality of control gate electrodes and each of the plurality of floating gate electrodes.
    Type: Grant
    Filed: September 6, 2012
    Date of Patent: January 6, 2015
    Assignee: SK Hynix Inc.
    Inventors: Sung-Jin Whang, Dong-Sun Sheen, Seung-Ho Pyi, Min-Soo Kim
  • Patent number: 8928063
    Abstract: A non-volatile memory device includes a channel layer vertically extending from a substrate, a plurality of inter-layer dielectric layers and a plurality of gate electrodes that are alternately stacked along the channel layer, and an air gap interposed between the channel layer and each of the plurality of gate electrodes. The non-volatile memory device may improve erase operation characteristics by suppressing back tunneling of electrons by substituting a charge blocking layer interposed between a gate electrode and a charge storage layer with an air gap, and a method for fabricating the non-volatile memory device.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: January 6, 2015
    Assignee: SK Hynix Inc.
    Inventors: Min-Soo Kim, Dong-Sun Sheen, Seung-Ho Pyi, Sung-Jin Whang
  • Patent number: 8860119
    Abstract: A nonvolatile memory device includes a substrate including a surface, a channel layer formed on the surface of the substrate, which protrudes perpendicularly from the surface, and a plurality of interlayer dielectric layers and a plurality of gate electrode layers alternately stacked along the channel layer, wherein the plurality of gate electrode layers protrude from the plurality of interlayer dielectric layers.
    Type: Grant
    Filed: September 5, 2012
    Date of Patent: October 14, 2014
    Assignee: SK Hynix Inc.
    Inventors: Min-Soo Kim, Dong-Sun Sheen, Seung-Ho Pyi, Sung-Jin Whang
  • Patent number: 8735962
    Abstract: A semiconductor device according to an embodiment of the present invention includes a vertical channel layer protruding upward from a semiconductor substrate, a tunnel insulating layer covering a sidewall of the vertical channel layer, a plurality of floating gates separated from each other and stacked one upon another along the vertical channel layer, and surrounding the vertical channel layer with the tunnel insulating layer interposed therebetween, a plurality of control gates enclosing the plurality of floating gates, respectively, and an interlayer insulating layer provided between the plurality of control gates.
    Type: Grant
    Filed: August 30, 2012
    Date of Patent: May 27, 2014
    Assignee: SK Hynix Inc.
    Inventors: Sung Jin Whang, Dong Sun Sheen, Seung Ho Pyi, Min Soo Kim
  • Publication number: 20130264629
    Abstract: A nonvolatile memory device includes a substrate; a channel layer projecting from a surface of the substrate, in a direction perpendicular to the surface; a tunnel dielectric layer surrounding the channel layer; a plurality of interlayer dielectric layers and a plurality of control gate electrodes alternately formed along the channel layer; floating gate electrodes interposed between the tunnel dielectric layer and the plurality of control gate electrodes, the floating gate electrodes comprising a metal-semiconductor compound; and a charge blocking layer interposed between each of the plurality of control gate electrodes and each of the plurality of floating gate electrodes.
    Type: Application
    Filed: September 6, 2012
    Publication date: October 10, 2013
    Inventors: Sung-Jin Whang, Dong-Sun Sheen, Seung-Ho Pyi, Min-Soo Kim