Patents by Inventor Dong-Sun Sheen

Dong-Sun Sheen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20130168752
    Abstract: A nonvolatile memory device includes a substrate including a surface, a channel layer formed on the surface of the substrate, which protrudes perpendicularly from the surface, and a plurality of interlayer dielectric layers and a plurality of gate electrode layers alternately stacked along the channel layer, wherein the plurality of gate electrode layers protrude from the plurality of interlayer dielectric layers.
    Type: Application
    Filed: September 5, 2012
    Publication date: July 4, 2013
    Inventors: Min-Soo KIM, Dong-Sun SHEEN, Seung-Ho PYI, Sung-Jin WHANG
  • Publication number: 20130161726
    Abstract: A non-volatile memory device includes a channel layer vertically extending from a substrate, a plurality of inter-layer dielectric layers and a plurality of gate electrodes that are alternately stacked along the channel layer, and an air gap interposed between the channel layer and each of the plurality of gate electrodes. The non-volatile memory device may improve erase operation characteristics by suppressing back tunneling of electrons by substituting a charge blocking layer interposed between a gate electrode and a charge storage layer with an air gap, and a method for fabricating the non-volatile memory device.
    Type: Application
    Filed: September 14, 2012
    Publication date: June 27, 2013
    Inventors: Min-Soo KIM, Dong-Sun SHEEN, Seung-Ho PYI, Sung-Jin WHANG
  • Publication number: 20130099304
    Abstract: The device includes plural control gates stacked on a substrate, plural first channels, configured to penetrate the control gates, and plural memory layer patterns, each located between the control gate and the first channel, configured to respectively surround the first channel, wherein the memory layer patterns are isolated from one another.
    Type: Application
    Filed: September 4, 2012
    Publication date: April 25, 2013
    Inventors: Min Soo KIM, Dong Sun Sheen, Young Jin Lee, Jin Hae Choi, Joo Hee Han, Sung Jin Whang
  • Publication number: 20130049095
    Abstract: A semiconductor device according to an embodiment of the present invention includes a vertical channel layer protruding upward from a semiconductor substrate, a tunnel insulating layer covering a sidewall of the vertical channel layer, a plurality of floating gates separated from each other and stacked one upon another along the vertical channel layer, and surrounding the vertical channel layer with the tunnel insulating layer interposed therebetween, a plurality of control gates enclosing the plurality of floating gates, respectively, and an interlayer insulating layer provided between the plurality of control gates.
    Type: Application
    Filed: August 30, 2012
    Publication date: February 28, 2013
    Applicant: SK HYNIX INC.
    Inventors: Sung Jin WHANG, Dong Sun SHEEN, Seung Ho PYI, Min Soo KIM
  • Patent number: 8330215
    Abstract: A method for fabricating a transistor including a bulb-type recess channel includes forming a bulb-type recess pattern in a substrate, forming a gate insulating layer over the substrate and the bulb-type recess pattern, forming a first gate conductive layer over the gate insulating layer, forming a void movement blocking layer over the first gate conductive layer in the bulb-type recess pattern, and forming a second gate conductive layer over the void movement blocking layer and the first gate conductive layer.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: December 11, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventors: Kwan-Yong Lim, Hong-Seon Yang, Dong-Sun Sheen, Se-Aug Jang, Heung-Jae Cho, Yong-Soo Kim, Min-Gyu Sung, Tae-Yoon Kim
  • Patent number: 8178921
    Abstract: A semiconductor device includes a semiconductor substrate having an active region which includes a gate forming zone and an isolation region; an isolation layer formed in the isolation region of the semiconductor substrate to expose side surfaces of a portion of the active region including the gate forming zone, such that the portion of the active region including the gate forming zone constitutes a fin pattern; a silicon epitaxial layer formed on the active region including the fin pattern; and a gate formed to cover the fin pattern on which the silicon epitaxial layer is formed.
    Type: Grant
    Filed: December 15, 2009
    Date of Patent: May 15, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventors: Dong Sun Sheen, Sang Tae Ahn, Seok Pyo Song, Hyeon Ju An
  • Publication number: 20120012928
    Abstract: A method for fabricating a transistor including a bulb-type recess channel includes forming a bulb-type recess pattern in a substrate, forming a gate insulating layer over the substrate and the bulb-type recess pattern, forming a first gate conductive layer over the gate insulating layer, forming a void movement blocking layer over the first gate conductive layer in the bulb-type recess pattern, and forming a second gate conductive layer over the void movement blocking layer and the first gate conductive layer.
    Type: Application
    Filed: September 23, 2011
    Publication date: January 19, 2012
    Inventors: Kwan-Yong Lim, Hong-Seon Yang, Dong-Sun Sheen, Se-Aug Jang, Heung-Jae Cho, Yong-Soo Kim, Min-Gyu Sung, Tae-Yoon Kim
  • Patent number: 8048742
    Abstract: A method for fabricating a transistor including a bulb-type recess channel includes forming a bulb-type recess pattern in a substrate, forming a gate insulating layer over the substrate and the bulb-type recess pattern, forming a first gate conductive layer over the gate insulating layer, forming a void movement blocking layer over the first gate conductive layer in the bulb-type recess pattern, and forming a second gate conductive layer over the void movement blocking layer and the first gate conductive layer.
    Type: Grant
    Filed: June 29, 2007
    Date of Patent: November 1, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventors: Kwan-Yong Lim, Hong-Seon Yang, Dong-Sun Sheen, Se-Aug Jang, Heung-Jae Cho, Yong-Soo Kim, Min-Gyu Sung, Tae-Yoon Kim
  • Patent number: 7888208
    Abstract: A method of fabricating a non-volatile memory device, A tunnel insulating layer, a floating gate, and a pad nitride layer is formed on a semiconductor substrate. A isolation region of the semiconductor substrate is formed by etching to a predetermined depth, and a liner insulating layer is formed on an entire surface of the resulting trench for device isolation. A filling insulation layer is formed on the liner insulating layer to fill the trench and a first etching process is performed on the filling insulation layer and the liner insulating layer. The surface of semiconductor is recessed by performing a second etching process on the filling insulation layer. A capping layer is formed on an entire surface of the result formed by the second etching process. The device isolation layer of a concave shape is formed by performing an etching process on the capping layer.
    Type: Grant
    Filed: June 30, 2008
    Date of Patent: February 15, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventors: Dong Sun Sheen, Seok Pyo Song
  • Patent number: 7795086
    Abstract: A method for manufacturing a semiconductor device using a salicide process, which includes forming a gate dielectric layer over a silicon substrate including a PMOS region and an NMOS region; forming a first silicon pattern in the NMOS region and a second silicon pattern in the PMOS region; forming a first metal layer that is in contact with the first silicon pattern and the exposed first portion of the silicon substrate; and forming a first gate, a first junction, a second gate, and a second junction by performing a heat treatment to silicify the respective first and second silicon patterns and the silicon substrate.
    Type: Grant
    Filed: December 30, 2008
    Date of Patent: September 14, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventors: Young Jin Lee, Dong Sun Sheen, Seok Pyo Song, Mi Ri Lee, Chi Ho Kim, Gil Jae Park, Bo Min Seo
  • Publication number: 20100090290
    Abstract: A semiconductor device includes a semiconductor substrate having an active region which includes a gate forming zone and an isolation region; an isolation layer formed in the isolation region of the semiconductor substrate to expose side surfaces of a portion of the active region including the gate forming zone, such that the portion of the active region including the gate forming zone constitutes a fin pattern; a silicon epitaxial layer formed on the active region including the fin pattern; and a gate formed to cover the fin pattern on which the silicon epitaxial layer is formed.
    Type: Application
    Filed: December 15, 2009
    Publication date: April 15, 2010
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventors: Dong Sun SHEEN, Sang Tae AHN, Seok Pyo SONG, Hyeon Ju AN
  • Patent number: 7687371
    Abstract: An isolation structure of a semiconductor device is formed by forming a hard mask layer on a semiconductor substrate having active and field regions to expose the field region. A trench is defined by etching the exposed field region of the semiconductor substrate using the hard mask as an etch mask. An SOG layer is formed in the trench partially filling the trench. An amorphous aluminum oxide layer is formed on the resultant substrate including the SOG layer. An HDP layer is formed on the amorphous aluminum oxide layer to completely fill the trench. The HDP layer and the amorphous aluminum oxide layer are subjected to CMP to expose the hard mask. The hard mask and portions of the amorphous aluminum oxide layer that are formed on the HDP layer are removed. The amorphous aluminum oxide layer is crystallized.
    Type: Grant
    Filed: October 1, 2008
    Date of Patent: March 30, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventors: Dong Sun Sheen, Seok Pyo Song, Sang Tae Ahn, Hyeon Ju An
  • Patent number: 7687362
    Abstract: A semiconductor device includes a semiconductor substrate having an active region including a channel portion. An isolation layer is formed in the semiconductor substrate to define the active region, and a gate is formed over the channel portion in the active region. The active region of the semiconductor substrate is etched to such that the entire active region is below an upper surface of the isolation layer. A U-shaped groove is formed in the channel portion of the active region, except the edges in a direction of the channel width thereof, in order to increase the channel width. In the semiconductor device, there is an increase in channel length and channel width leading to a reduction in leakage current and on increase in operation current.
    Type: Grant
    Filed: November 16, 2007
    Date of Patent: March 30, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventors: Seok Pyo Song, Dong Sun Sheen, Young Ho Lee
  • Patent number: 7687355
    Abstract: A method for manufacturing a fin transistor includes forming a trench by etching a semiconductor substrate. A flowable insulation layer is filled in the trench to form a field insulation layer defining an active region. The portion of the flowable insulation layer coming into contact with a gate forming region is etched so as to protrude the gate forming region in the active region. A protective layer over the semiconductor substrate is formed to fill the portion of the etched flowable insulation layer. The portion of the protective layer formed over the active region is removed to expose the active region of the semiconductor substrate. The exposed active region of the semiconductor substrate is cleaned. The protective layer remaining on the portion of the etched flowable insulation layer is removed. Gates are formed over the protruded gate forming regions in the active region.
    Type: Grant
    Filed: December 28, 2007
    Date of Patent: March 30, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventors: Dong Sun Sheen, Seok Pyo Song, Young Ho Lee
  • Patent number: 7655533
    Abstract: A semiconductor device includes a semiconductor substrate having an active region which includes a gate forming zone and an isolation region; an isolation layer formed in the isolation region of the semiconductor substrate to expose side surfaces of a portion of the active region including the gate forming zone, such that the portion of the active region including the gate forming zone constitutes a fin pattern; a silicon epitaxial layer formed on the active region including the fin pattern; and a gate formed to cover the fin pattern on which the silicon epitaxial layer is formed.
    Type: Grant
    Filed: July 12, 2007
    Date of Patent: February 2, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventors: Dong Sun Sheen, Sang Tae Ahn, Seok Pyo Song, Hyeon Ju An
  • Patent number: 7655534
    Abstract: A fin transistor is formed by forming a hard mask layer on a substrate having an active region and a field region. The hard mask layer is etched to expose the field region. A trench is formed by etching the exposed field region. The trench is filled with an SOG layer. The hard mask layer is removed to expose the active region. An epi-silicon layer is formed on the exposed active region. The SOG layer is then partially etched from the upper end of the trench, thus filling a lower portion of the trench. A HDP oxide layer is deposited on the etched SOG layer filling the trench, thereby forming a field oxide layer composed of the SOG layer and the HDP oxide. The HDP oxide layer in the field oxide layer is etched to expose both side surfaces of the epi-silicon layer. A gate is then formed on the epi-silicon layer of which both side surfaces are exposed and the field oxide layer.
    Type: Grant
    Filed: November 8, 2006
    Date of Patent: February 2, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventors: Dong Sun Sheen, Seok Pyo Song, Sang Tae Ahn, Hyun Chul Sohn
  • Patent number: 7585730
    Abstract: A method of fabricating a non-volatile memory device includes forming a tunneling layer and a conductive layer on a semiconductor substrate, and patterning the conductive layer, the tunneling layer, and the semiconductor substrate to form a conductive pattern, a tunneling pattern, and a trench in the semiconductor substrate. The method also includes filling the trench with a insulating material, and exposing a partial sidewall of the conductive pattern. The method further includes recessing the exposed partial sidewall of the conductive pattern in an inward direction to form a floating gate. The floating gate includes a base portion and a protruding portion having a width smaller than that of the base portion. The method also includes etching the insulating layer to form an isolation layer that exposes the base portion of the floating gate.
    Type: Grant
    Filed: June 30, 2008
    Date of Patent: September 8, 2009
    Assignee: Hynix Semiconductor Inc.
    Inventors: Seok Pyo Song, Dong Sun Sheen, Young Jin Lee, Mi Ri Lee, Chi Ho Kim, Gil Jae Park, Bo Min Seo
  • Publication number: 20090186456
    Abstract: A method for manufacturing a semiconductor device using a salicide process, which includes forming a gate dielectric layer over a silicon substrate including a PMOS region and an NMOS region; forming a first silicon pattern in the NMOS region and a second silicon pattern in the PMOS region; forming a first metal layer that is in contact with the first silicon pattern and the exposed first portion of the silicon substrate; and forming a first gate, a first junction, a second gate, and a second junction by performing a heat treatment to silicify the respective first and second silicon patterns and the silicon substrate.
    Type: Application
    Filed: December 30, 2008
    Publication date: July 23, 2009
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventors: Young Jin Lee, Dong Sun Sheen, Seok Pyo Song, Mi Ri Lee, Chi Ho Kim, Gil Jae Park, Bo Min Seo
  • Patent number: 7563654
    Abstract: A method for manufacturing a semiconductor device is disclosed. The method includes the steps of defining a trench into a field region of a semiconductor substrate having an active region and the field region; partially filing the trench with a flowable insulation layer; completely filling the trench with an isolation structure by depositing a close-packed insulation layer on the flowable insulation layer in the trench; etching through a portion of the close-packed insulation layer and etching into a partial thickness of the flowable insulation layer of the insulation structure to expose a portion of the active region; cleaning the resultant substrate having the active region relatively projected; forming spacers on etched portions of the flowable insulation layer where bowing occurs during the cleaning step; and forming gates on the active region and the insulation structure to border the exposed portion of the active region.
    Type: Grant
    Filed: December 29, 2006
    Date of Patent: July 21, 2009
    Assignee: Hynix Semiconductor Inc.
    Inventors: Dong Sun Sheen, Seok Pyo Song, Sang Tae Ahn, Hyeon Ju An, Hyun Chul Sohn
  • Publication number: 20090170283
    Abstract: A method of fabricating a non-volatile memory device, A tunnel insulating layer, a floating gate, and a pad nitride layer is formed on a semiconductor substrate. A isolation region of the semiconductor substrate is formed by etching to a predetermined depth, and a liner insulating layer is formed on an entire surface of the resulting trench for device isolation. A filling insulation layer is formed on the liner insulating layer to fill the trench and a first etching process is performed on the filling insulation layer and the liner insulating layer. The surface of semiconductor is recessed by performing a second etching process on the filling insulation layer. A capping layer is formed on an entire surface of the result formed by the second etching process. The device isolation layer of a concave shape is formed by performing an etching process on the capping layer.
    Type: Application
    Filed: June 30, 2008
    Publication date: July 2, 2009
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventors: Dong Sun Sheen, Seok Pyo Song