Patents by Inventor Dong-Sun Sheen

Dong-Sun Sheen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090163013
    Abstract: Provided is a method for forming a gate of a non-volatile memory device. A tunneling layer, a charge trapping layer, a blocking layer, and a control gate layer are formed on a semiconductor substrate. A hard mask is formed on the control gate layer. The hard mask defines a region on which a gate is formed. A gate pattern is formed by etching the control gate layer, the blocking layer, the charge trapping layer, and the tunneling layer. A damage compensation layer on a side of the gate pattern is formed using ultra low pressure plasma of a pressure range from approximately 1 mT to approximately 100 mT.
    Type: Application
    Filed: June 2, 2008
    Publication date: June 25, 2009
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventors: Seok Pyo Song, Dong Sun Sheen, Seung Ho Pyi, Ki Seon Park, Sun Hwan Hwang, Mi Ri Lee, Gil Jae Park
  • Patent number: 7538007
    Abstract: Disclosed is a semiconductor device with a flowable insulation layer formed on a capacitor and a method for fabricating the same. Particularly, the semiconductor device includes: a capacitor formed on a predetermined portion of a substrate; an insulation layer formed by stacking a flowable insulation layer and an undoped silicate glass layer on a resulting substrate structure including the substrate and the capacitor; and a metal interconnection line formed on the insulation layer. The method includes the steps of: forming a capacitor on a predetermined portion of a substrate; forming an insulation layer by stacking a flowable insulation layer and an undoped silicate glass layer on a resulting substrate structure including the substrate and the capacitor; and forming a metal interconnection line on the insulation layer.
    Type: Grant
    Filed: December 10, 2004
    Date of Patent: May 26, 2009
    Assignee: Hynix Semiconductor, Inc.
    Inventors: Sang-Tae Ahn, Dong-Sun Sheen, Seok-Pyo Song, Jong-Han Shin
  • Patent number: 7501687
    Abstract: An isolation structure of a semiconductor device is formed by forming a hard mask layer on a semiconductor substrate having active and field regions to expose the field region. A trench is defined by etching the exposed field region of the semiconductor substrate using the hard mask as an etch mask. An SOG layer is formed in the trench partially filling the trench. An amorphous aluminum oxide layer is formed on the resultant substrate including the SOG layer. An HDP layer is formed on the amorphous aluminum oxide layer to completely fill the trench. The HDP layer and the amorphous aluminum oxide layer are subjected to CMP to expose the hard mask. The hard mask and portions of the amorphous aluminum oxide layer that are formed on the HDP layer are removed. The amorphous aluminum oxide layer is crystallized.
    Type: Grant
    Filed: December 29, 2006
    Date of Patent: March 10, 2009
    Assignee: Hynix Semiconductor Inc.
    Inventors: Dong Sun Sheen, Seok Pyo Song, Sang Tae Ahn, Hyeon Ju An
  • Publication number: 20090029521
    Abstract: An isolation structure of a semiconductor device is formed by forming a hard mask layer on a semiconductor substrate having active and field regions to expose the field region. A trench is defined by etching the exposed field region of the semiconductor substrate using the hard mask as an etch mask. An SOG layer is formed in the trench partially filling the trench. An amorphous aluminum oxide layer is formed on the resultant substrate including the SOG layer. An HDP layer is formed on the amorphous aluminum oxide layer to completely fill the trench. The HDP layer and the amorphous aluminum oxide layer are subjected to CMP to expose the hard mask. The hard mask and portions of the amorphous aluminum oxide layer that are formed on the HDP layer are removed. The amorphous aluminum oxide layer is crystallized.
    Type: Application
    Filed: October 1, 2008
    Publication date: January 29, 2009
    Inventors: Dong Sun SHEEN, Seok Pyo SONG, Sang Tae AHN, Hyeon Ju AN
  • Publication number: 20090029523
    Abstract: The invention relates to a method of fabricating flash memory device. In accordance with an aspect of the invention, the method includes forming a gate insulating layer, a first conductive layer, and an isolation mask over a semiconductor substrate. The isolation mask is patterned to expose regions in which an isolation layer will be formed. The first conductive layer, the gate insulating layer, and the semiconductor substrate are etched using the patterned isolation mask to form trenches. A liner oxide layer is formed on the resulting structure including the trenches. The trenches in which the liner oxide layer is formed are filled with an insulating layer. A planarizing process and a cleaning process are carried out such that wing spacers covering the gate insulating layer are formed at top edge portions of the isolation layer, thereby forming the isolation layer.
    Type: Application
    Filed: July 24, 2008
    Publication date: January 29, 2009
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventors: Ji Hyun Seo, Seok Pyo Song, Dong Sun Sheen
  • Publication number: 20080242030
    Abstract: A method for manufacturing a fin transistor includes forming a trench by etching a semiconductor substrate. A flowable insulation layer is filled in the trench to form a field insulation layer defining an active region. The portion of the flowable insulation layer coming into contact with a gate forming region is etched so as to protrude the gate forming region in the active region. A protective layer over the semiconductor substrate is formed to fill the portion of the etched flowable insulation layer. The portion of the protective layer formed over the active region is removed to expose the active region of the semiconductor substrate. The exposed active region of the semiconductor substrate is cleaned. The protective layer remaining on the portion of the etched flowable insulation layer is removed. Gates are formed over the protruded gate forming regions in the active region.
    Type: Application
    Filed: December 28, 2007
    Publication date: October 2, 2008
    Inventors: Dong Sun SHEEN, Seok Pyo SONG, Young Ho LEE
  • Publication number: 20080224212
    Abstract: A method for fabricating a semiconductor device is provided. A first insulation layer and a second insulation layer are formed over the substrate having a gate. A spacer etching process is performed to form an etched first insulation layer and an etched second insulation layer. The etched first insulation layer partially protrudes from the substrate and contacts sidewalls of the gate. The etched second insulation layer is removed through a selective epitaxial growth (SEG) process that forms an epitaxial layer over the exposed substrate. One of facets of the epitaxial layer is formed on the protruding portion of the etched first insulation layer. A third insulation layer is formed on sidewalls of the etched first insulation layer and the one of the facets of the epitaxial layer is covered by the third insulation layer.
    Type: Application
    Filed: December 27, 2007
    Publication date: September 18, 2008
    Applicant: Hynix Semiconductor Inc.
    Inventors: Young-Ho LEE, Dong-Sun Sheen, Seok-Pyo Song
  • Publication number: 20080194104
    Abstract: An apparatus for use in a plasma chemical vapor deposition (CVD) includes a chamber; a cooling gas inlet passing through an electrostatic chuck for supplying a cooling gas to the bottom surface of a wafer when the plasma CVD process is performed; and a clamping unit for clamping the wafer to the electrostatic chuck when the cooling gas is supplied.
    Type: Application
    Filed: April 18, 2008
    Publication date: August 14, 2008
    Applicant: Hynix Semiconductor Inc.
    Inventors: Dong-Sun Sheen, Seok-Pyo Song, Sang-Tae Ahn
  • Publication number: 20080185663
    Abstract: A semiconductor device includes a semiconductor substrate having an active region including a channel portion. An isolation layer is formed in the semiconductor substrate to define the active region, and a gate is formed over the channel portion in the active region. The active region of the semiconductor substrate is etched to such that the entire active region is below an upper surface of the isolation layer. A U-shaped groove is formed in the channel portion of the active region, except the edges in a direction of the channel width thereof, in order to increase the channel width. In the semiconductor device, there is an increase in channel length and channel width leading to a reduction in leakage current and on increase in operation current.
    Type: Application
    Filed: November 16, 2007
    Publication date: August 7, 2008
    Inventors: Seok Pyo SONG, Dong Sun SHEEN, Young Ho LEE
  • Publication number: 20080079076
    Abstract: A semiconductor device includes a semiconductor substrate having an active region which includes a gate forming zone and an isolation region; an isolation layer formed in the isolation region of the semiconductor substrate to expose side surfaces of a portion of the active region including the gate forming zone, such that the portion of the active region including the gate forming zone constitutes a fin pattern; a silicon epitaxial layer formed on the active region including the fin pattern; and a gate formed to cover the fin pattern on which the silicon epitaxial layer is formed.
    Type: Application
    Filed: July 12, 2007
    Publication date: April 3, 2008
    Inventors: Dong Sun SHEEN, Sang Tae AHN, Seok Pyo SONG, Hyeon Ju AN
  • Publication number: 20080079093
    Abstract: A method for fabricating a transistor including a bulb-type recess channel includes forming a bulb-type recess pattern in a substrate, forming a gate insulating layer over the substrate and the bulb-type recess pattern, forming a first gate conductive layer over the gate insulating layer, forming a void movement blocking layer over the first gate conductive layer in the bulb-type recess pattern, and forming a second gate conductive layer over the void movement blocking layer and the first gate conductive layer.
    Type: Application
    Filed: June 29, 2007
    Publication date: April 3, 2008
    Inventors: Kwan-Yong Lim, Hong-Seon Yang, Dong-Sun Sheen, Se-Aug Jang, Heung-Jae Cho, Yong-Soo Kim, Min-Gyu Sung, Tae-Yoon Kim
  • Publication number: 20080001249
    Abstract: An isolation structure of a semiconductor device is formed by forming a hard mask layer on a semiconductor substrate having active and field regions to expose the field region. A trench is defined by etching the exposed field region of the semiconductor substrate using the hard mask as an etch mask. An SOG layer is formed in the trench partially filling the trench. An amorphous aluminum oxide layer is formed on the resultant substrate including the SOG layer. An HDP layer is formed on the amorphous aluminum oxide layer to completely fill the trench. The HDP layer and the amorphous aluminum oxide layer are subjected to CMP to expose the hard mask. The hard mask and portions of the amorphous aluminum oxide layer that are formed on the HDP layer are removed. The amorphous aluminum oxide layer is crystallized.
    Type: Application
    Filed: December 29, 2006
    Publication date: January 3, 2008
    Inventors: Dong Sun Sheen, Seok Pyo Song, Sang Tae Ahn, Hyeon Ju An
  • Publication number: 20070281454
    Abstract: A method for manufacturing a semiconductor device is disclosed. The method includes the steps of defining a trench into a field region of a semiconductor substrate having an active region and the field region; partially filing the trench with a flowable insulation layer; completely filling the trench with an isolation structure by depositing a close-packed insulation layer on the flowable insulation layer in the trench; etching through a portion of the close-packed insulation layer and etching into a partial thickness of the flowable insulation layer of the insulation structure to expose a portion of the active region; cleaning the resultant substrate having the active region relatively projected; forming spacers on etched portions of the flowable insulation layer where bowing occurs during the cleaning step; and forming gates on the active region and the insulation structure to border the exposed portion of the active region.
    Type: Application
    Filed: December 29, 2006
    Publication date: December 6, 2007
    Inventors: Dong Sun Sheen, Seok Pyo Song, Sang Tae Ahn, Hyeon Ju An, Hyun Chul Sohn
  • Publication number: 20070148840
    Abstract: A fin transistor is formed by forming a hard mask layer on a substrate having an active region and a field region. The hard mask layer is etched to expose the field region. A trench is formed by etching the exposed field region. The trench is filled with an SOG layer. The hard mask layer is removed to expose the active region. An epi-silicon layer is formed on the exposed active region. The SOG layer is then partially etched from the upper end of the trench, thus filling a lower portion of the trench. A HDP oxide layer is deposited on the etched SOG layer filling the trench, thereby forming a field oxide layer composed of the SOG layer and the HDP oxide. The HDP oxide layer in the field oxide layer is etched to expose both side surfaces of the epi-silicon layer. A gate is then formed on the epi-silicon layer of which both side surfaces are exposed and the field oxide layer.
    Type: Application
    Filed: November 8, 2006
    Publication date: June 28, 2007
    Inventors: Dong Sun Sheen, Seok Pyo Song, Sang Tae Ahn, Hyun Chul Sohn
  • Patent number: 7166519
    Abstract: The present invention relates to a method for isolating semiconductor devices. The method includes the steps of: forming a patterned pad nitride layer pattern to open at least one isolation region on the substrate; forming a first trench and a second trench by etching the exposed substrate; depositing a first oxide layer to fill the first trench by performing an atomic layer deposition (ALD) method; etching a portion of the first oxide layer which is filled into the wide trench; and depositing a second oxide layer by performing a deposition method.
    Type: Grant
    Filed: June 12, 2004
    Date of Patent: January 23, 2007
    Assignee: Hynix Semiconductor Inc.
    Inventors: Sang-Tae Ahn, Dong-Sun Sheen, Seok-Pyo Song
  • Patent number: 7087515
    Abstract: A method for forming a flowable dielectric layer using a barrier layer on sidewalls of patterned flowable dielectrics, thereby preventing a bridge phenomenon between adjacent contact plugs. The method includes steps of: forming patterns on a semiconductor substrate, wherein narrow and deep gaps are formed therebetween; forming a flowable dielectric layer so as to fill the gaps between the patterns; carrying out an annealing process for densifying the flowable dielectric layer and removing moisture therein; forming contact holes by selectively etching the flowable dielectric layer so as to expose predetermined portions of the semiconductor substrate; forming a barrier layer on sidewalls of the contact holes for preventing micro-pores in the flowable dielectric layer; carrying out a cleaning process in order to remove native oxides and defects on the semiconductor substrate; and forming contact plugs by filling a conductive material into the contact plugs.
    Type: Grant
    Filed: December 19, 2003
    Date of Patent: August 8, 2006
    Assignee: Hynix Semiconductor Inc.
    Inventors: Sang-Tae Ahn, Dong-Sun Sheen, Seok-Pyo Song
  • Publication number: 20060094218
    Abstract: An apparatus for use in a plasma chemical vapor deposition (CVD) includes a chamber; a cooling gas inlet passing through an electrostatic chuck for supplying a cooling gas to the bottom surface of a wafer when the plasma CVD process is performed; and a clamping unit for clamping the wafer to the electrostatic chuck when the cooling gas is supplied.
    Type: Application
    Filed: August 30, 2005
    Publication date: May 4, 2006
    Applicant: Hynix Semiconductor Inc.
    Inventors: Dong-Sun Sheen, Seok-Pyo Song, Sang-Tae Ahn
  • Publication number: 20050266650
    Abstract: Disclosed is a semiconductor device with a flowable insulation layer formed on a capacitor and a method for fabricating the same. Particularly, the semiconductor device includes: a capacitor formed on a predetermined portion of a substrate; an insulation layer formed by stacking a flowable insulation layer and an undoped silicate glass layer on a resulting substrate structure including the substrate and the capacitor; and a metal interconnection line formed on the insulation layer. The method includes the steps of: forming a capacitor on a predetermined portion of a substrate; forming an insulation layer by stacking a flowable insulation layer and an undoped silicate glass layer on a resulting substrate structure including the substrate and the capacitor; and forming a metal interconnection line on the insulation layer.
    Type: Application
    Filed: December 10, 2004
    Publication date: December 1, 2005
    Inventors: Sang-Tae Ahn, Dong-Sun Sheen, Seok-Pyo Song, Jong-Han Shin
  • Publication number: 20050142795
    Abstract: The present invention relates to a method for isolating semiconductor devices. The method includes the steps of: forming a patterned pad nitride layer pattern to open at least one isolation region on the substrate; forming a first trench and a second trench by etching the exposed substrate; depositing a first oxide layer to fill the first trench by performing an atomic layer deposition (ALD) method; etching a portion of the first oxide layer which is filled into the wide trench; and depositing a second oxide layer by performing a deposition method.
    Type: Application
    Filed: June 12, 2004
    Publication date: June 30, 2005
    Inventors: Sang-Tae Ahn, Dong-Sun Sheen, Seok-Pyo Song
  • Publication number: 20050020093
    Abstract: The method for forming a flowable dielectric layer is employed to use a barrier layer on sidewalls of patterned flowable dielectrics, thereby preventing a bridge phenomenon between adjacent contact plugs.
    Type: Application
    Filed: December 19, 2003
    Publication date: January 27, 2005
    Inventors: Sang-Tae Ahn, Dong-Sun Sheen, Seok-Pyo Song