Abstract: An apparatus for use in a plasma chemical vapor deposition (CVD) includes a chamber; a cooling gas inlet passing through an electrostatic chuck for supplying a cooling gas to the bottom surface of a wafer when the plasma CVD process is performed; and a clamping unit for clamping the wafer to the electrostatic chuck when the cooling gas is supplied.

Abstract: A semiconductor device includes a semiconductor substrate having an active region including a channel portion. An isolation layer is formed in the semiconductor substrate to define the active region, and a gate is formed over the channel portion in the active region. The active region of the semiconductor substrate is etched to such that the entire active region is below an upper surface of the isolation layer. A U-shaped groove is formed in the channel portion of the active region, except the edges in a direction of the channel width thereof, in order to increase the channel width. In the semiconductor device, there is an increase in channel length and channel width leading to a reduction in leakage current and on increase in operation current.

Abstract: A method for fabricating a transistor including a bulb-type recess channel includes forming a bulb-type recess pattern in a substrate, forming a gate insulating layer over the substrate and the bulb-type recess pattern, forming a first gate conductive layer over the gate insulating layer, forming a void movement blocking layer over the first gate conductive layer in the bulb-type recess pattern, and forming a second gate conductive layer over the void movement blocking layer and the first gate conductive layer.

Abstract: A semiconductor device includes a semiconductor substrate having an active region which includes a gate forming zone and an isolation region; an isolation layer formed in the isolation region of the semiconductor substrate to expose side surfaces of a portion of the active region including the gate forming zone, such that the portion of the active region including the gate forming zone constitutes a fin pattern; a silicon epitaxial layer formed on the active region including the fin pattern; and a gate formed to cover the fin pattern on which the silicon epitaxial layer is formed.

Abstract: An isolation structure of a semiconductor device is formed by forming a hard mask layer on a semiconductor substrate having active and field regions to expose the field region. A trench is defined by etching the exposed field region of the semiconductor substrate using the hard mask as an etch mask. An SOG layer is formed in the trench partially filling the trench. An amorphous aluminum oxide layer is formed on the resultant substrate including the SOG layer. An HDP layer is formed on the amorphous aluminum oxide layer to completely fill the trench. The HDP layer and the amorphous aluminum oxide layer are subjected to CMP to expose the hard mask. The hard mask and portions of the amorphous aluminum oxide layer that are formed on the HDP layer are removed. The amorphous aluminum oxide layer is crystallized.

Abstract: A method for manufacturing a semiconductor device is disclosed. The method includes the steps of defining a trench into a field region of a semiconductor substrate having an active region and the field region; partially filing the trench with a flowable insulation layer; completely filling the trench with an isolation structure by depositing a close-packed insulation layer on the flowable insulation layer in the trench; etching through a portion of the close-packed insulation layer and etching into a partial thickness of the flowable insulation layer of the insulation structure to expose a portion of the active region; cleaning the resultant substrate having the active region relatively projected; forming spacers on etched portions of the flowable insulation layer where bowing occurs during the cleaning step; and forming gates on the active region and the insulation structure to border the exposed portion of the active region.

Abstract: A fin transistor is formed by forming a hard mask layer on a substrate having an active region and a field region. The hard mask layer is etched to expose the field region. A trench is formed by etching the exposed field region. The trench is filled with an SOG layer. The hard mask layer is removed to expose the active region. An epi-silicon layer is formed on the exposed active region. The SOG layer is then partially etched from the upper end of the trench, thus filling a lower portion of the trench. A HDP oxide layer is deposited on the etched SOG layer filling the trench, thereby forming a field oxide layer composed of the SOG layer and the HDP oxide. The HDP oxide layer in the field oxide layer is etched to expose both side surfaces of the epi-silicon layer. A gate is then formed on the epi-silicon layer of which both side surfaces are exposed and the field oxide layer.

Abstract: The present invention relates to a method for isolating semiconductor devices. The method includes the steps of: forming a patterned pad nitride layer pattern to open at least one isolation region on the substrate; forming a first trench and a second trench by etching the exposed substrate; depositing a first oxide layer to fill the first trench by performing an atomic layer deposition (ALD) method; etching a portion of the first oxide layer which is filled into the wide trench; and depositing a second oxide layer by performing a deposition method.

Abstract: A method for forming a flowable dielectric layer using a barrier layer on sidewalls of patterned flowable dielectrics, thereby preventing a bridge phenomenon between adjacent contact plugs. The method includes steps of: forming patterns on a semiconductor substrate, wherein narrow and deep gaps are formed therebetween; forming a flowable dielectric layer so as to fill the gaps between the patterns; carrying out an annealing process for densifying the flowable dielectric layer and removing moisture therein; forming contact holes by selectively etching the flowable dielectric layer so as to expose predetermined portions of the semiconductor substrate; forming a barrier layer on sidewalls of the contact holes for preventing micro-pores in the flowable dielectric layer; carrying out a cleaning process in order to remove native oxides and defects on the semiconductor substrate; and forming contact plugs by filling a conductive material into the contact plugs.

Abstract: An apparatus for use in a plasma chemical vapor deposition (CVD) includes a chamber; a cooling gas inlet passing through an electrostatic chuck for supplying a cooling gas to the bottom surface of a wafer when the plasma CVD process is performed; and a clamping unit for clamping the wafer to the electrostatic chuck when the cooling gas is supplied.

Abstract: Disclosed is a semiconductor device with a flowable insulation layer formed on a capacitor and a method for fabricating the same. Particularly, the semiconductor device includes: a capacitor formed on a predetermined portion of a substrate; an insulation layer formed by stacking a flowable insulation layer and an undoped silicate glass layer on a resulting substrate structure including the substrate and the capacitor; and a metal interconnection line formed on the insulation layer. The method includes the steps of: forming a capacitor on a predetermined portion of a substrate; forming an insulation layer by stacking a flowable insulation layer and an undoped silicate glass layer on a resulting substrate structure including the substrate and the capacitor; and forming a metal interconnection line on the insulation layer.

Abstract: The present invention relates to a method for isolating semiconductor devices. The method includes the steps of: forming a patterned pad nitride layer pattern to open at least one isolation region on the substrate; forming a first trench and a second trench by etching the exposed substrate; depositing a first oxide layer to fill the first trench by performing an atomic layer deposition (ALD) method; etching a portion of the first oxide layer which is filled into the wide trench; and depositing a second oxide layer by performing a deposition method.

Abstract: The method for forming a flowable dielectric layer is employed to use a barrier layer on sidewalls of patterned flowable dielectrics, thereby preventing a bridge phenomenon between adjacent contact plugs.

Abstract: A method of manufacturing a semiconductor device is provided. A first interlayer insulating layer is formed on a silicon substrate, and a lower metal layer is formed on the first interlayer insulating layer. A first insulating layer is formed on the first interlayer insulating layer including the lower metal layer, moisture contained in the first insulating layer is removed by N.sub.2 or N.sub.2 O plasma. Thereafter, a SOG layer and a second insulating layer are sequentially formed on the first insulating layer.

Abstract: Disclosed herein is a method of manufacturing a semiconductor device, which comprises steps of forming metal patterns, irradiating an electron beam to electrically neutralize the charge distribution of the metal layer and forming an O.sub.3 -TEOS layer used for planarization of the interlayer insulating layer.