Patents by Inventor Dong-Uk Lee

Dong-Uk Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11416425
    Abstract: A memory includes: a first data bus; a second data bus; and a plurality of bank groups. The bank groups output read data by alternately using the first data bus and the second data bus during read operations of the bank groups. One of the plurality of bank groups transfer read data to the first data bus during a read operation based on an odd-numbered read command. Further, one of the plurality of bank groups transfer transfer one of the plurality of bank groups read data to the second data bus during a read operation based on an even-numbered read command.
    Type: Grant
    Filed: April 6, 2020
    Date of Patent: August 16, 2022
    Assignee: SK hynix Inc.
    Inventor: Dong-Uk Lee
  • Patent number: 11411017
    Abstract: A semiconductor device includes: a stack structure including gate patterns and insulating patterns; a channel layer penetrating the stack structure; a memory layer penetrating the stack structure, the memory layer surrounding the channel layer; and a select transistor connected to the channel layer. The select transistor includes: a carbon layer Schottky-joined with the channel layer; a select gate spaced apart from the carbon layer; and a gate insulating layer between the select gate and the carbon layer.
    Type: Grant
    Filed: July 29, 2020
    Date of Patent: August 9, 2022
    Assignee: SK hynix Inc.
    Inventors: Dong Uk Lee, Hae Chang Yang
  • Patent number: 11393549
    Abstract: A memory system includes a plurality of memory devices coupled to each other through a channel and each including a test clock input pad suitable for receiving an external test clock, a clock generation circuit suitable for generating an input clock and an output clock based on a reference clock and the external test clock in response to a reset signal, a test data processing circuit suitable for parallelizing test data so as to produce parallelized test data and transfer the parallelized test data to a memory area in response to the input clock and the output clock, and a test control signal generation circuit suitable for generating internal test data by serializing the parallelized test data and transferring the internal test data to the channel in response to the input clock and the output clock.
    Type: Grant
    Filed: October 21, 2020
    Date of Patent: July 19, 2022
    Assignee: SK hynix Inc.
    Inventor: Dong Uk Lee
  • Patent number: 11386965
    Abstract: There are provided a memory device, a memory system including the memory device, and an operating method of the memory system. The memory device includes a memory cell array including a plurality of memory blocks, a peripheral circuit for performing a read operation by applying a read voltage to a selected memory block among the plurality of memory blocks, and control logic for controlling the peripheral circuit to perform a normal read operation using initially set voltages and a read retry operation using new read voltages. The peripheral circuit performs the read retry operation by using the new read voltage corresponding to program states other than at least one program state included in a specific threshold voltage region among a plurality of program states of the selected memory block.
    Type: Grant
    Filed: October 11, 2019
    Date of Patent: July 12, 2022
    Assignee: SK hynix Inc.
    Inventor: Dong Uk Lee
  • Patent number: 11373699
    Abstract: An address and command generation circuit, and a semiconductor system are disclosed. The address and command generation circuit may include a column address generator configured to correct an error of a column address, generate an internal column address based on an uncorrected column address when the column address corresponds to a read command, and generate the internal column address based on the corrected column address when the column address corresponds to a write command.
    Type: Grant
    Filed: August 21, 2020
    Date of Patent: June 28, 2022
    Assignee: SK hynix Inc.
    Inventors: Dong Uk Lee, Ji Hwan Kim, Heat Bit Park
  • Publication number: 20220187633
    Abstract: A film, in which a phase transition material is not applied on an entire surface thereof and a pattern form is provided so that the aesthetically superior film of which a color is not cloudy but bright may be obtained and which has a high visible light transmittance as well as superior thermochromic properties, and a smart window including the same.
    Type: Application
    Filed: March 5, 2021
    Publication date: June 16, 2022
    Applicant: LMS Co., Ltd.
    Inventors: Dong Uk LEE, Ho Seong NA, Ji Tae KIM, Jong Yoon LEE, Sang Hyun YOON, Seong Yong YOON, Mi Young PARK
  • Publication number: 20220189568
    Abstract: The present technology relates to an electronic device. A memory device that controls a voltage applied to each line to prevent or mitigate a channel negative boosting phenomenon during a sensing operation includes a memory block connected to a plurality of lines, a peripheral circuit configured to perform a sensing operation on selected memory cells connected to a selected word line among the plurality of lines, and control logic configured to control voltages applied to drain select lines, source select lines, and word lines between the drain select lines and the source select lines among the plurality of lines, during the sensing operation and an equalizing operation performed after the sensing operation. The control logic controls a voltage applied to an unselected drain select line according to whether a cell string is shared with a selected drain select line among the drain select lines, during the sensing operation.
    Type: Application
    Filed: June 24, 2021
    Publication date: June 16, 2022
    Applicant: SK hynix Inc.
    Inventors: Dong Uk LEE, Hae Chang YANG, Hun Wook LEE
  • Patent number: 11355207
    Abstract: A memory device, and a method of operating the memory device, includes a memory block configured to include a plurality of memory cells that are stacked to be spaced apart from each other on a substrate and to include word lines coupled to the plurality of memory cells, and bit lines and a source line coupled to both ends of strings including the plurality of memory cells, and peripheral circuits configured to perform an erase operation on the memory block, wherein the peripheral circuits are configured to perform the erase operation on the plurality of memory cells included in the memory block, and thereafter perform a defect detection operation on memory cells selected from among the plurality of memory cells depending on sizes of the plurality of memory cells.
    Type: Grant
    Filed: August 26, 2020
    Date of Patent: June 7, 2022
    Assignee: SK hynix Inc.
    Inventors: Dong Uk Lee, Hae Chang Yang
  • Patent number: 11355168
    Abstract: A stacked semiconductor device includes a base die including an input buffer and a parallel circuit; and a plurality of core dies stacked over the base die, the core dies coupled to the base die through a plurality of through-electrodes, wherein the input buffer receives write data in a first order and a write inversion signal, the parallel circuit sorts consecutive bits of the write data to be positioned adjacent to each other so that the write data becomes first parallel data and to transfer the first parallel data to respective first to n-th internal input/output lines, and each of the core dies includes an input control circuit to re-sort the first parallel data transferred via the respective first to n-th internal I/O lines into the write data and a write inversion circuit to selectively invert the re-sorted write data according to the write inversion signal.
    Type: Grant
    Filed: September 4, 2020
    Date of Patent: June 7, 2022
    Assignee: SK hynix Inc.
    Inventor: Dong Uk Lee
  • Publication number: 20220135012
    Abstract: An integrated braking device for a vehicle equipped with wheel brakes includes a reservoir, master cylinder, bi-directional pumps each using hydraulic pressure oil from the reservoir for generating hydraulic pressure in first direction to apply braking force to the wheel brakes or generating hydraulic pressure in opposing second direction to control the hydraulic pressure oil from flowing to the reservoir, a hydraulic motor for driving the bi-directional pumps, inlet valves for controlling a hydraulic pressure from flowing from the bi-directional pumps to the wheel brakes, traction control valves each disposed between the master cylinder and each bi-directional pump to control flow of the hydraulic pressure oil inside the master cylinder, and a braking control unit for braking the vehicle by transmitting a driving signal to solenoid valves in the integrated braking device, the bi-directional pumps, and the hydraulic motor to control a flow of the hydraulic pressure.
    Type: Application
    Filed: December 22, 2020
    Publication date: May 5, 2022
    Inventor: Dong Uk LEE
  • Patent number: 11312185
    Abstract: Provided is a tire capable of efficiently discharging water, which is additionally absorbed through a plurality of flow tubes, through the flow tubes and a drain tube, thereby improving wet grip performance. The tire with enhanced wet grip includes a kerf formed on a block to discharge water introduced thereinto to a groove, a drain tube formed in the kerf in its longitudinal direction and connected to the groove to discharge the water to the groove, and a flow tube formed in the kerf toward the drain tube from an inlet of the kerf, into which the water is introduced, and connected to the groove or the drain tube.
    Type: Grant
    Filed: December 3, 2018
    Date of Patent: April 26, 2022
    Assignee: Hankook Tire Co., Ltd.
    Inventors: Jae Gang Park, Dong Uk Lee, Ha Eun Koog
  • Patent number: 11309436
    Abstract: A semiconductor memory device includes, a stack structure, and a channel structure passing through the stack structure, wherein the channel structure includes a channel layer passing through the stack structure and a memory layer surrounding the channel layer, the stack structure includes a gate contacting the channel layer, and the channel layer and the gate form a Schottky junction.
    Type: Grant
    Filed: April 2, 2020
    Date of Patent: April 19, 2022
    Assignee: SK hynix Inc.
    Inventors: Dong Uk Lee, Hae Chang Yang
  • Publication number: 20220093194
    Abstract: A controller including a test manager configured to output a program command for performing a program operation of a memory block and a suspend command for stopping the program operation, and a memory interface configured to transmit the program command to a memory device including the memory block, and transmit the suspend command to the memory device after a set time elapses. The test manager outputs a read command for reading memory cells included in the memory block, the memory interface calculates a count value by counting data output from the memory device in response to the read command, and the test manager generates status information on the memory block according to the count value.
    Type: Application
    Filed: March 22, 2021
    Publication date: March 24, 2022
    Applicant: SK hynix Inc.
    Inventors: Dong Uk LEE, Hae Chang YANG, Hun Wook LEE
  • Publication number: 20220068960
    Abstract: A semiconductor memory device and methods of manufacturing and operating the same are set forth. The semiconductor memory device includes a stack structure including a plurality of interlayer insulating layers and a plurality of gate electrodes, which may be alternately stacked on a substrate, and a plurality of channel structures penetrating the stack structure in a vertical direction. Each of the plurality of channel structures includes a channel layer, a tunnel insulating layer, an emission preventing layer, and a charge storage layer, each of which vertically extends toward the substrate.
    Type: Application
    Filed: February 11, 2021
    Publication date: March 3, 2022
    Applicant: SK hynix Inc.
    Inventors: Dong Uk LEE, Hae Chang YANG
  • Patent number: 11152042
    Abstract: An inversion signal generation circuit may include a transition detection signal generation circuit suitable for generating first to fourth transition detection signals, a first XOR gate suitable for receiving a fourth inversion signal and the first transition detection signal, and generating a first pre-inversion signal, a second XOR gate suitable for receiving the first pre-inversion signal and the second transition detection signal, and generating a second pre-inversion signal, a third XOR gate suitable for receiving the second transition detection signal and the third transition detection signal, a fourth XOR gate suitable for receiving the first pre-inversion signal and an output signal of the third XOR gate, and generating a third pre-inversion signal, a fifth XOR gate suitable for receiving the third pre-inversion signal and the fourth transition detection signal, and generating a fourth pre-inversion signal, and a first alignment circuit suitable for generating first to fourth inversion signals.
    Type: Grant
    Filed: August 7, 2020
    Date of Patent: October 19, 2021
    Assignee: SK hynix Inc.
    Inventor: Dong Uk Lee
  • Publication number: 20210304831
    Abstract: A memory device, and a method of operating the memory device, includes a memory block configured to include a plurality of memory cells that are stacked to be spaced apart from each other on a substrate and to include word lines coupled to the plurality of memory cells, and bit lines and a source line coupled to both ends of strings including the plurality of memory cells, and peripheral circuits configured to perform an erase operation on the memory block, wherein the peripheral circuits are configured to perform the erase operation on the plurality of memory cells included in the memory block, and thereafter perform a defect detection operation on memory cells selected from among the plurality of memory cells depending on sizes of the plurality of memory cells.
    Type: Application
    Filed: August 26, 2020
    Publication date: September 30, 2021
    Applicant: SK hynix Inc.
    Inventors: Dong Uk LEE, Hae Chang YANG
  • Publication number: 20210304802
    Abstract: A stacked semiconductor device includes a base die including an input buffer and a parallel circuit; and a plurality of core dies stacked over the base die, the core dies coupled to the base die through a plurality of through-electrodes, wherein the input buffer receives write data in a first order and a write inversion signal, the parallel circuit sorts consecutive bits of the write data to be positioned adjacent to each other so that the write data becomes first parallel data and to transfer the first parallel data to respective first to n-th internal input/output lines, and each of the core dies includes an input control circuit to re-sort the first parallel data transferred via the respective first to n-th internal I/O lines into the write data and a write inversion circuit to selectively invert the re-sorted write data according to the write inversion signal.
    Type: Application
    Filed: September 4, 2020
    Publication date: September 30, 2021
    Inventor: Dong Uk LEE
  • Publication number: 20210295940
    Abstract: A memory system includes a plurality of memory devices coupled to each other through a channel and each including a test clock input pad suitable for receiving an external test clock, a clock generation circuit suitable for generating an input clock and an output clock based on a reference clock and the external test clock in response to a reset signal, a test data processing circuit suitable for parallelizing test data so as to produce parallelized test data and transfer the parallelized test data to a memory area in response to the input clock and the output clock, and a test control signal generation circuit suitable for generating internal test data by serializing the parallelized test data and transferring the internal test data to the channel in response to the input clock and the output clock.
    Type: Application
    Filed: October 21, 2020
    Publication date: September 23, 2021
    Inventor: Dong Uk LEE
  • Publication number: 20210272969
    Abstract: A semiconductor device includes: a stack structure including gate patterns and insulating patterns; a channel layer penetrating the stack structure; a memory layer penetrating the stack structure, the memory layer surrounding the channel layer; and a select transistor connected to the channel layer. The select transistor includes: a carbon layer Schottky-joined with the channel layer; a select gate spaced apart from the carbon layer; and a gate insulating layer between the select gate and the carbon layer.
    Type: Application
    Filed: July 29, 2020
    Publication date: September 2, 2021
    Applicant: SK hynix Inc.
    Inventors: Dong Uk LEE, Hae Chang YANG
  • Publication number: 20210272970
    Abstract: A switching element comprising: a first gate dielectric layer formed over a substrate; a second gate dielectric layer formed over the first gate dielectric layer to overlap a part of the first gate dielectric layer, and including a ferroelectric material; a second gate electrode formed over the second gate dielectric layer; and a first gate electrode located between the first and second gate dielectric layers, and configured to control the second gate dielectric layer to selectively have negative capacitance.
    Type: Application
    Filed: February 23, 2021
    Publication date: September 2, 2021
    Applicant: SK hynix Inc.
    Inventors: Dong Uk LEE, Hae Chang YANG