Abstract: In one example, a semiconductor device can comprise a substrate, a device stack, first and second internal interconnects, and an encapsulant. The substrate can comprise a first and second substrate sides opposite each other, a substrate outer sidewall between the first substrate side and the second substrate side, and a substrate inner sidewall defining a cavity between the first substrate side and the second substrate side. The device stack can be in the cavity and can comprise a first electronic device, and a second electronic device stacked on the first electronic device. The first internal interconnect can be coupled to the substrate and the device stack. The encapsulant can cover the substrate inner sidewall and the device stack and can fill the cavity. Other examples and related methods are disclosed herein.

Abstract: In an embodiment, an apparatus is disclosed that includes a duty cycle controller. The duty cycle controller includes a tuning circuit comprising a first field-effect transistor. The first field-effect transistor is configured to implement a capacitor. The duty cycle controller further includes an edge delay circuit. The edge delay circuit includes a second field-effect transistor that, when activated by an input clock signal of the duty cycle controller, is configured to connect a voltage source to an output clock signal of the duty cycle controller. The edge delay circuit further includes a third field-effect transistor that, when activated, is configured to connect the first field-effect transistor of the tuning circuit to the output clock signal.

Abstract: An apparatus is disclosed that includes a duty cycle controller. The duty cycle controller includes a tuning circuit comprising a first field-effect transistor. The first field-effect transistor is configured to implement a capacitor. The duty cycle controller further includes an edge delay circuit. The edge delay circuit includes a second field-effect transistor that, when activated by an input clock signal of the duty cycle controller, is configured to connect a voltage source to an output clock signal of the duty cycle controller. The edge delay circuit further includes a third field-effect transistor that, when activated, is configured to connect the first field-effect transistor of the tuning circuit to the output clock signal.

Abstract: In an embodiment, an apparatus is disclosed that includes a duty cycle controller. The duty cycle controller includes a tuning circuit comprising a first field-effect transistor. The first field-effect transistor is configured to implement a capacitor. The duty cycle controller further includes an edge delay circuit. The edge delay circuit includes a second field-effect transistor that, when activated by an input clock signal of the duty cycle controller, is configured to connect a voltage source to an output clock signal of the duty cycle controller. The edge delay circuit further includes a third field-effect transistor that, when activated, is configured to connect the first field-effect transistor of the tuning circuit to the output clock signal.

Abstract: An apparatus for controlling an object may include a communicator configured to communicate with a first user terminal and a second user terminal, and a processor configured to control a first object corresponding to a first user in a virtual world to be displayed, configured to control the first object to move in the virtual world in response to a movement control of the first user, configured to randomly select at least one candidate object in response to a morphing control of the first user, and configured to change the first object to a second object when the first user selects the second object from the at least one candidate object. Methods for controlling an object are also provided.

Abstract: An apparatus for controlling an object may include a communicator configured to communicate with a first user terminal and a second user terminal, and a processor configured to control a first object corresponding to a first user in a virtual world to be displayed, configured to control the first object to move in the virtual world in response to a movement control of the first user, configured to randomly select at least one candidate object in response to a morphing control of the first user, and configured to change the first object to a second object when the first user selects the second object from the at least one candidate object. Methods for controlling an object are also provided.

Abstract: An apparatus for controlling an object may include a communicator configured to communicate with a first user terminal and a second user terminal, and a processor configured to control a first object corresponding to a first user in a virtual world to be displayed, configured to control the first object to move in the virtual world in response to a movement control of the first user, configured to randomly select at least one candidate object in response to a morphing control of the first user, and configured to change the first object to a second object when the first user selects the second object from the at least one candidate object. Methods for controlling an object are also provided.

Abstract: An apparatus for controlling an object may include a communicator configured to communicate with a first user terminal and a second user terminal, and a processor configured to control a first object corresponding to a first user in a virtual world to be displayed, configured to control the first object to move in the virtual world in response to a movement control of the first user, configured to randomly select at least one candidate object in response to a morphing control of the first user, and configured to change the first object to a second object when the first user selects the second object from the at least one candidate object. Methods for controlling an object are also provided.

Abstract: Various embodiments of the invention allow for error calibration in analog-to-digital converters (ADCs) having multiple cascaded ADC stages. The ADC stages exchange information that is utilized in the calibration process. Various embodiments allow for calibration of one stage by utilizing a feedback signal from at least one subsequent stage. Certain embodiments of the invention increase the speed of the calibration process by utilizing coarse and fine sub-ADCs.

Abstract: A gain controller using switched capacitors is provided. The gain controller is operable in a sampling mode or an amplifying mode and controls the gain of an analog input signal. The gain controller includes an operational amplifier, input capacitors, a feedback capacitor, and switches. The operational amplifier controls the gain of the analog input signal and generates an output signal having the controlled gain. The input capacitors are connected to the input side of the operational amplifier in parallel. The feedback capacitor is connected between the input side and the output side of the operational amplifier. The switches connect at least one of the input capacitors to the input signal or a reference voltage, in response to the kinds of operation modes and a predetermined externally applied digital gain control signal.

Abstract: A gain controller using switched capacitors is provided. The gain controller is operable in a sampling mode or an amplifying mode and controls the gain of an analog input signal. The gain controller includes an operational amplifier, input capacitors, a feedback capacitor, and switches. The operational amplifier controls the gain of the analog input signal and generates an output signal having the controlled gain. The input capacitors are connected to the input side of the operational amplifier in parallel. The feedback capacitor is connected between the input side and the output side of the operational amplifier. The switches connect at least one of the input capacitors to the input signal or a reference voltage, in response to the kinds of operation modes and a predetermined externally applied digital gain control signal.

Abstract: A gain controller using switched capacitors is provided. The gain controller is operable in a sampling mode or an amplifying mode and controls the gain of an analog input signal. The gain controller includes an operational amplifier, input capacitors, a feedback capacitor, and switches. The operational amplifier controls the gain of the analog input signal and generates an output signal having the controlled gain. The input capacitors are connected to the input side of the operational amplifier in parallel. The feedback capacitor is connected between the input side and the output side of the operational amplifier. The switches connect at least one of the input capacitors to the input signal or a reference voltage, in response to the kinds of operation modes and a predetermined externally applied digital gain control signal.

Abstract: An analog/digital (A/D) converting circuit is provided that stabilizes system operation, reduces power consumption in an analog circuit region and uses a selected metal-to-metal capacitor, which has a small parasitic capacitance value. The A/D converting circuit includes a first sample/hold amplifier for sampling/holding an analog input signal, a switch for selecting one of a signal outputted from the first sample/hold amplifier and a feedback signal and an A/D sub-converter for converting an analog signal outputted from the switch to a digital signal. A multiplying D/A converting block converts an output signal from the A/D sub-converter to an analog signal and amplifies a difference value obtained between the analog signal and the analog signal outputted from the switch. A second sample/hold amplifier samples/holds a signal outputted from the multiplying D/A converting block and outputs the feedback signal to the switch.

Abstract: Operational amplifier integrated circuits include a differential input stage, a cascode current mirror, a cascode current source and a preferred bias signal generator which is responsive to a clock signal and is electrically coupled to the differential input stage, the cascode current mirror and the cascode current source. This preferred bias signal generator sequentially enables the cascode current mirror and then the differential input stage in response to a rising edge of the clock signal and disables the cascode current mirror and the cascode current source in response to a falling edge of the clock signal. This sequential enablement of the cascode current mirror before the differential input stage improves the unity gain phase margin characteristics of the circuit and the disablement of the cascode current mirror and the cascode current source in response to the falling edge of the clock signal decreases the power consumption requirements of the circuit.