Patents by Inventor Dongqing Yang

Dongqing Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180337057
    Abstract: Exemplary semiconductor processing systems may include a processing chamber, and may include a remote plasma unit coupled with the processing chamber. Exemplary systems may also include an adapter coupled with the remote plasma unit. The adapter may include a first end and a second end opposite the first end. The adapter may define a central channel through the adapter. The adapter may define an exit from a second channel at the second end, and the adapter may define an exit from a third channel at the second end. The central channel, the second channel, and the third channel may each be fluidly isolated from one another within the adapter.
    Type: Application
    Filed: May 17, 2017
    Publication date: November 22, 2018
    Applicant: Applied Materials, Inc.
    Inventors: Mehmet Tugrul Samir, Dongqing Yang, Dmitry Lubomirsky, Peter Hillman, Soonam Park, Martin Yue Choy, Lala Zhu
  • Publication number: 20180337074
    Abstract: Exemplary support assemblies may include a top puck and a backing plate coupled with the top puck. The support assemblies may include a cooling plate coupled with the backing plate. The support assemblies may include a heater coupled between the cooling plate and the backing plate. The support assemblies may also include a back plate coupled with the backing plate about an exterior of the backing plate. The back plate may at least partially define a volume, and the heater and the cooling plate may be housed within the volume.
    Type: Application
    Filed: May 17, 2017
    Publication date: November 22, 2018
    Applicant: Applied Materials, Inc.
    Inventors: Mehmet Tugrul Samir, Dongqing Yang, Dmitry Lubomirsky, Peter Hillman, Soonam Park, Martin Yue Choy, Lala Zhu
  • Publication number: 20180337021
    Abstract: Embodiments of the present disclosure generally provide improved methods for processing substrates with improved process stability, increased mean wafers between clean, and/or improved within wafer uniformity. One embodiment provides a method for seasoning one or more chamber components in a process chamber. The method includes placing a dummy substrate in the process chamber, flowing a processing gas mixture to the process chamber to react with the dummy substrate and generate a byproduct on the dummy substrate, and annealing the dummy substrate to sublimate the byproduct while at least one purge conduit of the process chamber is closed.
    Type: Application
    Filed: June 5, 2018
    Publication date: November 22, 2018
    Inventors: Sang Won Kang, Nicholas Celeste, Dmitry Lubomirsky, Peter Hillman, Douglas Brenton Hayden, Dongqing Yang
  • Patent number: 10134581
    Abstract: Methods for forming a spacer comprising depositing a film on the top, bottom and sidewalls of a feature and treating the film to change a property of the film on the top and bottom of the feature. Selectively dry etching the film from the top and bottom of the feature relative to the film on the sidewalls of the feature using a high intensity plasma.
    Type: Grant
    Filed: March 10, 2017
    Date of Patent: November 20, 2018
    Assignee: Applied Materials, Inc.
    Inventors: Ning Li, Mihaela Balseanu, Li-Qun Xia, Dongqing Yang, Anchuan Wang
  • Publication number: 20180211833
    Abstract: Processing platforms having a central transfer station with a robot and an environment having greater than or equal to about 0.1% by weight water vapor, a pre-clean chamber connected to a side of the transfer station and a batch processing chamber connected to a side of the transfer station. The processing platform configured to pre-clean a substrate to remove native oxides from a first surface, form a blocking layer using a alkylsilane and selectively deposit a film. Methods of using the processing platforms and processing a plurality of wafers are also described.
    Type: Application
    Filed: January 24, 2018
    Publication date: July 26, 2018
    Inventors: Ning Li, Mihaela Balseanu, Li-Qun Xia, Dongqing Yang, Lala Zhu, Malcolm J. Bevan, Theresa Kramer Guarini, Wenbo Yan
  • Patent number: 10008366
    Abstract: Embodiments of the present disclosure generally provide improved methods for processing substrates with improved process stability, increased mean wafers between clean, and/or improved within wafer uniformity. One embodiment provides a method for seasoning one or more chamber components in a process chamber. The method includes placing a dummy substrate in the process chamber, flowing a processing gas mixture to the process chamber to react with the dummy substrate and generate a byproduct on the dummy substrate, and annealing the dummy substrate to sublimate the byproduct while at least one purge conduit of the process chamber is closed.
    Type: Grant
    Filed: September 8, 2016
    Date of Patent: June 26, 2018
    Assignee: Applied Materials, Inc.
    Inventors: Sang Won Kang, Nicholas Celeste, Dmitry Lubomirsky, Peter Hillman, Douglas Brenton Hayden, Dongqing Yang
  • Publication number: 20170263438
    Abstract: Methods for forming a spacer comprising depositing a film on the top, bottom and sidewalls of a feature and treating the film to change a property of the film on the top and bottom of the feature. Selectively dry etching the film from the top and bottom of the feature relative to the film on the sidewalls of the feature using a high intensity plasma.
    Type: Application
    Filed: March 10, 2017
    Publication date: September 14, 2017
    Inventors: Ning Li, Mihaela Balseanu, Li-Qun Xia, Dongqing Yang, Anchuan Wang
  • Patent number: 9721789
    Abstract: Methods of selectively removing silicon oxide are described. Exposed portions of silicon oxide and spacer material may both be present on a patterned substrate. The silicon oxide may be a native oxide formed on silicon by exposure to atmosphere. The exposed portion of spacer material may have been etched back using reactive ion etching (RIE). A portion of the exposed spacer material may have residual damage from the reactive ion etching. A self-assembled monolayer (SAM) is selectively deposited over the damaged portion of spacer material but not on the exposed silicon oxide or undamaged portions of spacer material. A subsequent gas-phase etch may then be used to selectively remove silicon oxide but not the damaged portion of the spacer material because the SAM has been found to not only preferentially adsorb on the damaged spacer but also to halt the etch rate.
    Type: Grant
    Filed: October 24, 2016
    Date of Patent: August 1, 2017
    Assignee: Applied Materials, Inc.
    Inventors: Dongqing Yang, Lala Zhu, Fei Wang, Nitin K. Ingle
  • Publication number: 20170194430
    Abstract: The present disclosure provides methods for forming nanowire spacers for nanowire structures with desired materials in horizontal gate-all-around (hGAA) structures for semiconductor chips. In one example, a method of forming nanowire spaces for nanowire structures on a substrate includes performing a lateral etching process on a substrate having a multi-material layer disposed thereon, wherein the multi-material layer including repeating pairs of a first layer and a second layer, the first and second layers each having a first sidewall and a second sidewall respectively exposed in the multi-material layer, wherein the lateral etching process predominately etches the second layer through the second layer forming a recess in the second layer, filling the recess with a dielectric material, and removing the dielectric layer over filled from the recess.
    Type: Application
    Filed: December 30, 2016
    Publication date: July 6, 2017
    Inventors: Bingxi Sun WOOD, Michael G. WARD, Shiyu SUN, Michael CHUDZIK, Nam Sung KIM, Hua CHUNG, Yi-Chiau HUANG, Chentsau YING, Ying ZHANG, Chi-Nung NI, Lin DONG, Dongqing YANG
  • Patent number: 9659753
    Abstract: A plasma source includes a first electrode and a second electrode having respective surfaces, and an insulator that is between and in contact with the electrodes. The electrode surfaces and the insulator surface substantially define a plasma cavity. The insulator surface defines one or more grooves configured to prevent deposition of material in a contiguous form on the insulator surface. A method of generating a plasma includes introducing one or more gases into a plasma cavity defined by a first electrode, a surface of an insulator that is in contact with the first electrode, and a second electrode that faces the first electrode. The insulator surface defines one or more grooves where portions of the insulator surface are not exposed to a central region of the cavity. The method further includes providing RF energy across the first and second electrodes to generate the plasma within the cavity.
    Type: Grant
    Filed: August 7, 2014
    Date of Patent: May 23, 2017
    Assignee: Applied Materials, Inc.
    Inventors: Tae Cho, Sang Won Kang, Dongqing Yang, Raymond W. Lu, Peter Hillman, Nicholas Celeste, Tien Fak Tan, Soonam Park, Dmitry Lubomirsky
  • Publication number: 20170069463
    Abstract: Embodiments of the present disclosure generally provide improved methods for processing substrates with improved process stability, increased mean wafers between clean, and/or improved within wafer uniformity. One embodiment provides a method for seasoning one or more chamber components in a process chamber. The method includes placing a dummy substrate in the process chamber, flowing a processing gas mixture to the process chamber to react with the dummy substrate and generate a byproduct on the dummy substrate, and annealing the dummy substrate to sublimate the byproduct while at least one purge conduit of the process chamber is closed.
    Type: Application
    Filed: September 8, 2016
    Publication date: March 9, 2017
    Inventors: Sang Won KANG, Nicholas CELESTE, Dmitry LUBOMIRSKY, Peter HILLMAN, Douglas Brenton HAYDEN, Dongqing YANG
  • Publication number: 20160042920
    Abstract: A plasma source includes a first electrode and a second electrode having respective surfaces, and an insulator that is between and in contact with the electrodes. The electrode surfaces and the insulator surface substantially define a plasma cavity. The insulator surface defines one or more grooves configured to prevent deposition of material in a contiguous form on the insulator surface. A method of generating a plasma includes introducing one or more gases into a plasma cavity defined by a first electrode, a surface of an insulator that is in contact with the first electrode, and a second electrode that faces the first electrode. The insulator surface defines one or more grooves where portions of the insulator surface are not exposed to a central region of the cavity. The method further includes providing RF energy across the first and second electrodes to generate the plasma within the cavity.
    Type: Application
    Filed: August 7, 2014
    Publication date: February 11, 2016
    Applicant: Applied Materials, Inc.
    Inventors: TAE CHO, Sang Won Kang, Dongqing Yang, Raymond W. Lu, Peter Hillman, Nicholas Celeste, Tien Fak Tan, Soonam Park, Dmitry Lubomirsky
  • Publication number: 20150311089
    Abstract: Methods of selectively etching tungsten oxide relative to tungsten, silicon oxide, silicon nitride and/or titanium nitride are described. The methods include a remote plasma etch formed from a fluorine-containing precursor and/or hydrogen (H2). Plasma effluents from the remote plasma are flowed into a substrate processing region where the plasma effluents react with the tungsten oxide. The plasmas effluents react with exposed surfaces and selectively remove tungsten oxide while very slowly removing other exposed materials. In some embodiments, the tungsten oxide selectivity results partly from the presence of an ion suppression element positioned between the remote plasma and the substrate processing region. The ion suppression element reduces or substantially eliminates the number of ionically-charged species that reach the substrate.
    Type: Application
    Filed: June 22, 2015
    Publication date: October 29, 2015
    Inventors: Sang Hyuk Kim, Dongqing Yang, Young S. Lee, Weon Young Jung, Sang-jin Kim, Ching-Mei Hsu, Anchuan Wang, Nitin K. Ingle
  • Patent number: 9064816
    Abstract: Methods of selectively etching tungsten oxide relative to tungsten, silicon oxide, silicon nitride and/or titanium nitride are described. The methods include a remote plasma etch formed from a fluorine-containing precursor and/or hydrogen (H2). Plasma effluents from the remote plasma are flowed into a substrate processing region where the plasma effluents react with the tungsten oxide. The plasmas effluents react with exposed surfaces and selectively remove tungsten oxide while very slowly removing other exposed materials. In some embodiments, the tungsten oxide selectivity results partly from the presence of an ion suppression element positioned between the remote plasma and the substrate processing region. The ion suppression element reduces or substantially eliminates the number of ionically-charged species that reach the substrate.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: June 23, 2015
    Assignee: Applied Materials, Inc.
    Inventors: Sang Hyuk Kim, Dongqing Yang, Young S. Lee, Weon Young Jung, Sang-jin Kim, Ching-Mei Hsu, Anchuan Wang, Nitin K. Ingle
  • Publication number: 20140199850
    Abstract: Methods of selectively etching tungsten oxide relative to tungsten, silicon oxide, silicon nitride and/or titanium nitride are described. The methods include a remote plasma etch formed from a fluorine-containing precursor and/or hydrogen (H2). Plasma effluents from the remote plasma are flowed into a substrate processing region where the plasma effluents react with the tungsten oxide. The plasmas effluents react with exposed surfaces and selectively remove tungsten oxide while very slowly removing other exposed materials. In some embodiments, the tungsten oxide selectivity results partly from the presence of an ion suppression element positioned between the remote plasma and the substrate processing region. The ion suppression element reduces or substantially eliminates the number of ionically-charged species that reach the substrate.
    Type: Application
    Filed: March 15, 2013
    Publication date: July 17, 2014
    Applicant: APPLIED MATERIALS, INC.
    Inventors: Sang Hyuk Kim, Dongqing Yang, Young S. Lee, Weon Young Jung, Sang-jin Kim, Ching-Mei Hsu, Anchuan Wang, Nitin K. Ingle
  • Patent number: 8741778
    Abstract: A method of etching silicon oxide from a multiple trenches is described which allows more homogeneous etch rates among trenches. The surfaces of the etched silicon oxide within the trench following the etch may also be smoother. The method includes two dry etch stages followed by a sublimation step. The first dry etch stage removes silicon oxide quickly and produces large solid residue granules. The second dry etch stage remove silicon oxide slowly and produces small solid residue granules in amongst the large solid residue granules. Both the small and large solid residue are removed in the ensuing sublimation step. There is no sublimation step between the two dry etch stages.
    Type: Grant
    Filed: August 3, 2011
    Date of Patent: June 3, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Dongqing Yang, Jing Tang, Nitin Ingle
  • Patent number: 8501629
    Abstract: A method of etching silicon-containing material is described and includes a SiConi™ etch having a greater or lesser flow ratio of hydrogen compared to fluorine than that found in the prior art. Modifying the flow rate ratios in this way has been found to reduce roughness of the post-etch surface and to reduce the difference in etch-rate between densely and sparsely patterned areas. Alternative means of reducing post-etch surface roughness include pulsing the flows of the precursors and/or the plasma power, maintaining a relatively high substrate temperature and performing the SiConi™ in multiple steps. Each of these approaches, either alone or in combination, serve to reduce the roughness of the etched surface by limiting solid residue grain size.
    Type: Grant
    Filed: December 23, 2009
    Date of Patent: August 6, 2013
    Assignee: Applied Materials, Inc.
    Inventors: Jing Tang, Nitin Ingle, Dongqing Yang
  • Patent number: 8475674
    Abstract: Methods of dry etching silicon-containing dielectric films are described. The methods include maintaining a relatively high temperature of the dielectric films while etching in order to achieve reduced solid residue on the etched surface. Partially or completely avoiding the accumulation of solid residue increases the etch rate.
    Type: Grant
    Filed: July 20, 2010
    Date of Patent: July 2, 2013
    Assignee: Applied Materials, Inc.
    Inventors: Kiran V. Thadani, Jing Tang, Nitin Ingle, Dongqing Yang
  • Patent number: 8435902
    Abstract: A method of etching silicon oxide from a narrow trench and a wide trench (or open area) is described which allows the etch in the wide trench to progress further than the etch in the narrow trench. The method includes two dry etch cycles. The first dry etch cycle involves a low intensity or abbreviated sublimation step which leaves solid residue in the narrow trench. The remaining solid residue inhibits etch progress in the narrow trench during the second dry etch cycle allowing the etch in the wide trench to overtake the etch in the narrow trench.
    Type: Grant
    Filed: December 2, 2010
    Date of Patent: May 7, 2013
    Assignee: Applied Materials, Inc.
    Inventors: Jing Tang, Nitin Ingle, Dongqing Yang, Shankar Venkataraman
  • Publication number: 20120196447
    Abstract: A method of etching silicon oxide from a multiple trenches is described which allows more homogeneous etch rates among trenches. The surfaces of the etched silicon oxide within the trench following the etch may also be smoother. The method includes two dry etch stages followed by a sublimation step. The first dry etch stage removes silicon oxide quickly and produces large solid residue granules. The second dry etch stage remove silicon oxide slowly and produces small solid residue granules in amongst the large solid residue granules. Both the small and large solid residue are removed in the ensuing sublimation step. There is no sublimation step between the two dry etch stages.
    Type: Application
    Filed: August 3, 2011
    Publication date: August 2, 2012
    Applicant: Applied Materials, Inc.
    Inventors: Dongqing Yang, Jing Tang, Nitin Ingle