Patents by Inventor Doo Hyung CHO

Doo Hyung CHO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220020671
    Abstract: The present invention minimizes parasitic inductance at the time of packaging a semiconductor that requires high efficiency and high-speed switching driving. In implementing a semiconductor package composed of one or more switching devices and one or more diode devices, the present invention provides a flip-stack structure in which a switching device is mounted on an insulating substrate or a metal frame, a flat metal is bonded onto the switching device, and a diode device is flipped and stacked on the flat metal, and accordingly, the flat metal with a large area is used for connection between the devices and between the devices and the insulating substrate, thereby minimizing parasitic inductance generated at a time of semiconductor packaging and automating the entire process of the semiconductor packaging.
    Type: Application
    Filed: July 20, 2021
    Publication date: January 20, 2022
    Applicant: Electronics and Telecommunications Research Institute
    Inventors: Dong Yun JUNG, Hyun Gyu JANG, Sung Kyu KWON, Kun Sik PARK, Jong Il WON, Seong Hyun LEE, Jong Won LIM, Doo Hyung CHO
  • Publication number: 20210408265
    Abstract: The present invention forms an off-FET channel having a uniform and short length by using a self-align process of a method of forming and recessing a spacer, thereby enhancing the current driving capability of an off-FET and the uniformity of a device operation.
    Type: Application
    Filed: June 23, 2021
    Publication date: December 30, 2021
    Applicant: Electronics and Telecommunications Research Institute
    Inventors: Kun Sik PARK, Jong Il WON, Doo Hyung CHO, Hyun Gyu JANG, Dong Yun JUNG
  • Publication number: 20210335681
    Abstract: A ceramic stacked semiconductor package and a method of packaging a ceramic stacked semiconductor is disclosed. Inner walls of junctions are formed between ceramic layers and a molding resin to have a non-uniform boundary shape (e.g., Z shape, an uneven shape, a zigzag shape, etc.) so that bonding areas and lengths of the molding resin and the ceramic layers are increased, and thus adhesion is improved and movement paths of moisture are increased, thereby improving anti-humidity property and reliability of the semiconductor package. Further, by arranging via-holes at different positions for each layer so as not to overlap each other between the layers, movement paths of moisture passing through the via-holes are increased, and thus the anti-humidity property and reliability of the stacked package are additionally improved.
    Type: Application
    Filed: March 30, 2021
    Publication date: October 28, 2021
    Applicant: Electronics and Telecommunications Research Institute
    Inventors: Hyun Gyu JANG, Dong Yun JUNG, Doo Hyung CHO, Kun Sik PARK, Jong Won LIM
  • Publication number: 20160284872
    Abstract: Provided is a Schottky diode including a substrate, a drift layer on the substrate, the drift layer comprising an active region and a periphery positioned at an edge of the active region, a junction termination layer on a boundary between the active region and the periphery, a first metal layer configured to cover a part of the active region and a part of the junction termination layer, and a second metal layer configured to cover the first metal layer and the active region, wherein the first metal layer and the second metal layer contact the drift layer to provide a Schottky junction, and the first metal layer has a higher Schottky barrier height than the second metal layer.
    Type: Application
    Filed: March 24, 2016
    Publication date: September 29, 2016
    Inventors: Kun Sik PARK, Jong II WON, Doo Hyung CHO