Patents by Inventor Doris Schmitt-Landsiedel
Doris Schmitt-Landsiedel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20030218481Abstract: A differential current evaluation circuit has a differential amplifier and a circuit for setting an input resistance of the current evaluation circuit. The circuit is connected to the outputs and the inputs of the differential amplifier and to signal lines. A sense amplifier circuit has a circuit section, in which a signal is available at an output in a temporally continuous manner even if, after the deactivation of the circuit connected upstream, a signal, in particular a signal supplied by the current evaluation circuit, is no longer present at its input. The differential current evaluation circuit and the sense amplifier circuit are disposed in a circuit configuration for reading out and evaluating a memory state of a semiconductor memory cell. The current evaluation circuit can be activated by a circuit section for automatic deactivation before a read operation and be automatically deactivated directly after the read operation has ended.Type: ApplicationFiled: May 2, 2003Publication date: November 27, 2003Inventors: Bernhard Wicht, Doris Schmitt-Landsiedel, Jean-Yves Larguier
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Publication number: 20020135044Abstract: A circuit configuration for providing a capacitance includes short-channel MOS transistors that are reverse-connected in series or in parallel, and that have the same channel type. When the short-channel MOS transistors are operated exclusively in the depletion mode in the required voltage range, the useful capacitance is increased, because of intrinsic capacitances, as compared with circuit configurations having conventional long-channel MOS transistors. These circuits greatly reduce the area taken up and reduce the costs.Type: ApplicationFiled: April 1, 2002Publication date: September 26, 2002Inventors: Thomas Tille, Doris Schmitt-Landsiedel, Jens Sauerbrey
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Patent number: 6323728Abstract: A data carrier includes at least one coil for the contactless reception of amplitude-modulated signals. A rectifier circuit is connected downstream of the coil. A circuit configuration processes and/or stores data. A supply-voltage control circuit is connected in parallel with the circuit configuration. A current measuring device acts as an amplitude demodulator and is disposed between the coil and the voltage-supply control circuit.Type: GrantFiled: September 5, 2000Date of Patent: November 27, 2001Assignee: Infineon Technologies AGInventors: Doris Schmitt-Landsiedel, Gerhard Schraud, Robert Reiner, Volker Güngerich
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Patent number: 6181183Abstract: A circuit with a delay stage formed by an invertor having high-impedance transistors and, connected in series therewith, an invertor having low-impedance transistors MOS capacitors are provided between the gates of the transistors of the low-impedance invertor and the output of the delay stage. By means of this circuit, delay stages with steep edges can be realized with comparatively less outlay on components.Type: GrantFiled: March 18, 1999Date of Patent: January 30, 2001Assignee: Siemens AktiengesellschaftInventors: Paul-Werner Von Basse, Roland Thewes, Michael Bollu, Doris Schmitt-Landsiedel
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Patent number: 6138227Abstract: A digital memory matrix having memory cells in rows and columns, addressing of the memory cells is accomplished by control devices which perform arbitrary jumps of address, thereby avoiding addressing on adjacent lines. The jump increment is selectable. The control devices are control chains, two of which are provided, and the outputs of the control chains are connected to linking elements that in turn are connected to the memory lines. The linking elements are provided in groups.Type: GrantFiled: March 13, 1998Date of Patent: October 24, 2000Assignee: Siemens AktiengesellschaftInventors: Roland Thewes, Doris Schmitt-Landsiedel, Paul-Werner von Basse, Michael Bollu
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Patent number: 6097661Abstract: In the pointer circuit, only one static memory (1) is respectively individually allocated to each output ( . . . , A.sub.n-1, A.sub.n, A.sub.n+1, . . . ), of which each respectively has a pair of mutually complementary memory terminals (Q, Q). The two terminals are in two stored logical states ("1," "0") differing from one another. A memory terminal (Q) of each memory is connected with the output allocated to this memory. The memories are controlled by clock signals. This results in advantageous surface requirement and power loss low, as well as high speed.Type: GrantFiled: September 25, 1998Date of Patent: August 1, 2000Assignee: Siemens AktiengesellschaftInventors: Roland Thewes, Doris Schmitt-Landsiedel, Paul-Werner von Basse, Michael Bollu, Ute Kollmer, Andreas Luck, deceased, by Manfred Luck, legal representative, by Inge Booken, legal representative
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Patent number: 6037885Abstract: A digital/analog converter has a neuron MOS transistor, a maintenance circuit which keeps the drain potential of the neuron MOS transistor constant, and a current source. A linear dynamic range in terms of large signal is possible, so that converters having a larger input word size than, for example, only two bits can be realized in a simple way with low dissipated power. Such converters are of significance particularly for ULSI circuits.Type: GrantFiled: January 14, 1998Date of Patent: March 14, 2000Assignee: Siemens AktiengesellschaftInventors: Doris Schmitt-Landsiedel, Roland Thewes, Doktorand Andreas Luck, Werner Weber
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Patent number: 5942912Abstract: A defined zero point voltage (V.sub.0), dependent on a settable zero point voltage target value (V.sub.0,soll), is enabled in amplifier stages (1 . . . k) with neuron MOS transistors (T10,1 . . . T10,k). This is generally required because, for example, due to a process-caused charging of the floating gates of the neuron MOS transistors, and due to a capacitively coupled-in voltage from the channel region, an undefined zero point displacement of the transmission characteristic curve results. The devices can be used together with the amplifier stages, e.g. in video and audio technology, in sensor technology, in analog computers, in fuzzy circuits and in neural networks.Type: GrantFiled: July 25, 1997Date of Patent: August 24, 1999Assignee: Siemens AktiengesellschaftInventors: Roland Thewes, Werner Weber, Andreas Luck, Doris Schmitt-Landsiedel
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Patent number: 5939945Abstract: Amplifier circuits having at least one neuron MOS transistor in which a coupling gate is connected to an amplifier output and at least one further coupling gate is connected with a respective amplifier input are provided. The amplifier circuit exhibits a linear transmission behavior even in large-signal operation and can be constructed using relatively few components. Furthermore, the gain is easy to set.Type: GrantFiled: July 25, 1997Date of Patent: August 17, 1999Assignee: Siemens AktiengesellschaftInventors: Roland Thewes, Werner Weber, Andreas Luck, Erdmute Wohlrab, Doris Schmitt-Landsiedel
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Patent number: 5831892Abstract: A matrix memory with improved virtual ground architecture and evaluation circuit from which the informational content of two neighboring memory cells can be simultaneously read at a bit line during a read event. The memory cells with information "0" are realized, for example, by a respective field effect transistor with low threshold voltage. Every bit line provided for the readout is connected to the drain terminals of two neighboring field effect transistors in the same row. The source terminals are applied to one of two potentials that differ from one another. Depending upon which of the field effect transistors is conductive upon selection of the pertinent word line, different resultant potentials are obtained on the bit line. Such potentials are then converted in the evaluation circuit into binary signals that represent the read information.Type: GrantFiled: August 1, 1997Date of Patent: November 3, 1998Assignee: Siemens AktiengesellschaftInventors: Roland Thewes, Paul-Werner von Basse, Michael Bollu, Doris Schmitt-Landsiedel
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Patent number: 5825686Abstract: The invention concerns a multi-valued read-only storage location which is constructed symmetrically for storing a first or second state (M, M"') and asymmetrically for storing at least a third state (M', M"). The advantage thereof is above all that the storage capacity is doubled without notably increasing expenditure and without impairing the signal-to-noise ratio with respect to conventional storage locations. The invention is suitable for electrically programmable and mask-programmable read-only memories, in particular for those used in low voltage technology.Type: GrantFiled: August 11, 1997Date of Patent: October 20, 1998Assignee: Siemens AktiengesellschaftInventors: Doris Schmitt-Landsiedel, Roland Thewes, Michael Bollu, Paul-Werner von Basse
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Patent number: 5825701Abstract: The memory cell arrangement has MOS transistors (10) connected between bitlines (4, 4.sub.1) and connected row-by-row by means of selection lines (5). For pre-charging of all the bitlines (4, 4.sub.1) without a blocking of an access to these lines, further MOS transistors (20), connected between the bitlines (4, 4.sub.1) and a supply line (7), are provided, whose gate terminals (20.sub.2) are connected to a common pre-charging line (6).Type: GrantFiled: July 16, 1996Date of Patent: October 20, 1998Assignee: Siemens AktiengesellschaftInventors: Paul-Werner Von Basse, Roland Thewes, Doris Schmitt-Landsiedel, Michael Bollu
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Patent number: 5798657Abstract: The bidirectional driver circuit for PCI bus system involves minimal circuit outlay. It is manufactured in a 3.3 technology and is essentially also operated only with 3.3 V, but is suited for a 5 V signal environment. The driver circuit has at least one selection logic (AL), a control circuit (A), a p-channel MOS transistor (M113), a first, second and third n-channel MOS transistor (M110, M111, M112). The advantage of the driver circuit is in its minimal circuit outlay.Type: GrantFiled: September 27, 1996Date of Patent: August 25, 1998Assignee: Siemens AktiengesellschaftInventors: Gerhard Nebel, Vincent Frechet, Doris Schmitt-Landsiedel
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Patent number: 5751742Abstract: In a serially working memory unit with a memory matrix, a row selection unit and a column selection unit are configured such that, given faulty rows or columns, only correctable, single errors or errors of few successive bits occur. This memory unit offers advantages particularly for read-only memories since, due to the memory contents that are already determined during manufacture, substitute rows or columns can thereby not be provided.Type: GrantFiled: April 2, 1996Date of Patent: May 12, 1998Assignee: Siemens AktiengesellschaftInventors: Paul-Werner Von Basse, Michael Bollu, Roland Thewes, Doris Schmitt-Landsiedel
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Patent number: 5732013Abstract: A matrix memory with memory transistors arranged in rows and columns. The memory transistors can be addressed via word lines and bit lines. Control transistors are driven via control lines. The control transistors can short-circuit all of the columns of the cell array, i.e. the bit lines, except for the column in which a memory cell is located which is to be read out.Type: GrantFiled: January 8, 1997Date of Patent: March 24, 1998Assignee: Siemens AktiengesellschaftInventors: Paul-Werner Von Basse, Roland Thewes, Doris Schmitt-Landsiedel, Michael Bollu
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Patent number: 5710448Abstract: An integrated polysilicon diode contact having multiple doped layers. A first highly doped layer of a first dopant type is deposited on a silicon substrate. A second highly doped layer of a second, different dopant type is deposited on the substrate, separated by a spacer from the first highly doped layer. A third lower doped layer of the second dopant type is deposited on the first highly doped layer and second highly doped layers, the third lower doped layer forming a p-n junction with a source region having a dopant of the first type.Type: GrantFiled: October 27, 1995Date of Patent: January 20, 1998Assignee: Siemens AktiengesellschaftInventors: Wolfgang H. Krautschneider, Doris Schmitt-Landsiedel, Werner Klingenstein
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Patent number: 5394034Abstract: A programmable logic array includes configurable logic cells disposed in lines and columns. Each of the logic cells has signal inputs, control inputs, at least one signal output, and an output driver circuit connected upstream of the at least one signal output. The output driver circuit has a terminal for a first and a second supply potential and is connected to at least one of the control inputs. The output driver circuit is controllable for setting its driver capacity to a level other than zero, corresponding to a signal value, by a digital signal applied to the at least one control input. Conductor tracks and switching elements for interconnecting the conductor tracks connect the at least one signal output of each of the logic cells to at least one of the signal inputs of at least another one of the logic cells.Type: GrantFiled: July 27, 1993Date of Patent: February 28, 1995Assignee: Siemens AktiengesellschaftInventors: Steffen Becker, Doris Schmitt-Landsiedel, Doris Keitel-Schulz
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Patent number: 5371423Abstract: A tri-state capable driver circuit or totem pole circuit is formed in BiCMOS technology and includes a selection circuit, first and second drive circuits, and first and second bipolar transistors. A short circuit unit is connected between the base and the emitter of the first bipolar transistor to prevent excessively high inhibit voltages across the base-emitter junction of the first bipolar transistor. The operation of the short circuit unit depends upon signals received at the tri-state activation input.Type: GrantFiled: August 17, 1993Date of Patent: December 6, 1994Assignee: Siemens AktiengesellschaftInventors: Joerg Berthold, Gerhard Nebel, Doris Schmitt-Landsiedel
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Patent number: 5170375Abstract: A static memory is constructed in a plurality of hierarchy levels. Beneficial realization possibilities are set forth with respect to the surface utilization for the drive and read-out circuits in the second hierarchy level which are especially critical. Memory cells that supply a strong cell signal are advantageously utilized so that a low expense is needed in the read circuit. By displacing periphery circuits into higher hierarchy levels, a short access time and a reduced surface requirement arise.Type: GrantFiled: September 18, 1991Date of Patent: December 8, 1992Assignee: Siemens AktiengesellschaftInventors: Hans-Juergen Mattausch, Bernhard Hoppe, Gerd Neuendorf, Doris Schmitt-Landsiedel, Hans-Joerg Pfleiderer, Maria Wurm
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Patent number: 5093809Abstract: Static memory having pipeline registers. The static memory has a plurality of hierarchy levels connected by pipeline registers. This architecture is very beneficial since the area requirements for the drive and read-out circuits in the first hierarchy level are especially critical. Advantageously, memory cells are used which have write and read word lines as well as separate write and read data lines and which also supply a strong cell signal so that only a few components are needed for the read circuit. A new clock format with an arrangement of pipeline registers is proposed for the appertaining memory for which power consumption is reduced by disconnecting the clocks in the lower hierarchy levels, resulting in increased area savings.Type: GrantFiled: March 5, 1990Date of Patent: March 3, 1992Assignee: Siemens AktiengesellschaftInventors: Doris Schmitt-Landsiedel, Bernhard Hoppe, Gerd Neuendorf, Maria Wurm