Patents by Inventor Doris Tzu Lang Chen
Doris Tzu Lang Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11171652Abstract: A method of configuring a programmable integrated circuit device. A channel source within the virtual fabric is configured to receive input data from a first kernel outside of the virtual fabric and on the programmable integrated circuit device, and a channel sink within the virtual fabric is configured to transmit output data to the first kernel. The configuring of the channel source is modified such that the channel source receives input data from a second kernel in response to detecting a change in operation of the programmable integrated circuit device.Type: GrantFiled: March 27, 2020Date of Patent: November 9, 2021Assignee: Altera CorporationInventors: Doris Tzu Lang Chen, Deshanand Singh
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Publication number: 20200228121Abstract: A method of configuring a programmable integrated circuit device. A channel source within the virtual fabric is configured to receive input data from a first kernel outside of the virtual fabric and on the programmable integrated circuit device, and a channel sink within the virtual fabric is configured to transmit output data to the first kernel. The configuring of the channel source is modified such that the channel source receives input data from a second kernel in response to detecting a change in operation of the programmable integrated circuit device.Type: ApplicationFiled: March 27, 2020Publication date: July 16, 2020Inventors: Doris Tzu Lang Chen, Deshanand Singh
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Patent number: 10615800Abstract: A method of configuring a programmable integrated circuit device. A channel source within the virtual fabric is configured to receive input data from a first kernel outside of the virtual fabric and on the programmable integrated circuit device, and a channel sink within the virtual fabric is configured to transmit output data to the first kernel. The configuring of the channel source is modified such that the channel source receives input data from a second kernel in response to detecting a change in operation of the programmable integrated circuit device.Type: GrantFiled: January 22, 2019Date of Patent: April 7, 2020Assignee: Altera CorporationInventors: Doris Tzu Lang Chen, Deshanand Singh
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Patent number: 10366189Abstract: A method of preparing a programmable integrated circuit device for configuration using a high-level language includes compiling a plurality of virtual programmable devices from descriptions in said high-level language. That compiling includes compiling configurations of configurable routing resources from programmable resources of said programmable integrated circuit device, and compiling configurations of a plurality of complex function blocks from programmable resources of said programmable integrated circuit device. A machine-readable data storage medium may be encoded with a library of such compiled configurations. A virtual programmable device may include a stall signal network and routing switches of the virtual programmable device may include stall signal inputs and outputs.Type: GrantFiled: August 15, 2016Date of Patent: July 30, 2019Assignee: Altera CorporationInventors: Doris Tzu-Lang Chen, Deshanand Singh
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Patent number: 10224934Abstract: A method of configuring a programmable integrated circuit device. A channel source within the virtual fabric is configured to receive input data from a first kernel outside of the virtual fabric and on the programmable integrated circuit device, and a channel sink within the virtual fabric is configured to transmit output data to the first kernel. The configuring of the channel source is modified such that the channel source receives input data from a second kernel in response to detecting a change in operation of the programmable integrated circuit device.Type: GrantFiled: November 15, 2016Date of Patent: March 5, 2019Assignee: Altera CorporationInventors: Doris Tzu Lang Chen, Deshanand Singh
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Patent number: 9548740Abstract: A method of configuring an integrated circuit device to perform a function includes storing a plurality of configurations for performing the function, each of the configurations being designed for a different characteristic of a particular input to the function. Inputs are received for the function, including the particular input. The characteristic of the particular input as received is examined, and one of the plurality of configurations is instantiated based on that characteristic of the particular input as received. A machine-readable data storage medium may be encoded with instructions to perform the method. A programmable device may be configured according to the method, and also may be incorporated into a heterogeneous system.Type: GrantFiled: September 9, 2013Date of Patent: January 17, 2017Assignee: Altera CorporationInventors: Doris Tzu-Lang Chen, Deshanand Singh
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Patent number: 9515658Abstract: A method of configuring a programmable integrated circuit device. A channel source within the virtual fabric is configured to receive input data from a first kernel outside of the virtual fabric and on the programmable integrated circuit device, and a channel sink within the virtual fabric is configured to transmit output data to the first kernel. The configuring of the channel source is modified such that the channel source receives input data from a second kernel in response to detecting a change in operation of the programmable integrated circuit device.Type: GrantFiled: October 9, 2014Date of Patent: December 6, 2016Assignee: Altera CorporationInventors: Doris Tzu Lang Chen, Deshanand Singh
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Publication number: 20160350452Abstract: A method of preparing a programmable integrated circuit device for configuration using a high-level language includes compiling a plurality of virtual programmable devices from descriptions in said high-level language. That compiling includes compiling configurations of configurable routing resources from programmable resources of said programmable integrated circuit device, and compiling configurations of a plurality of complex function blocks from programmable resources of said programmable integrated circuit device. A machine-readable data storage medium may be encoded with a library of such compiled configurations. A virtual programmable device may include a stall signal network and routing switches of the virtual programmable device may include stall signal inputs and outputs.Type: ApplicationFiled: August 15, 2016Publication date: December 1, 2016Inventors: Doris Tzu-Lang Chen, Deshanand Singh
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Patent number: 9449132Abstract: A method of preparing a programmable integrated circuit device for configuration using a high-level language includes compiling a plurality of virtual programmable devices from descriptions in said high-level language. the compiling includes compiling configurations of configurable routing resources from programmable resources of said programmable integrated circuit device, and compiling configurations of a plurality of complex function blocks from programmable resources of said programmable integrated circuit device. A machine-readable data storage medium may be encoded with a library of such compiled configurations. A virtual programmable device may include a stall signal network and routing switches of the virtual programmable device may include stall signal inputs and outputs.Type: GrantFiled: January 6, 2015Date of Patent: September 20, 2016Assignee: Altera CorporationInventors: Doris Tzu-Lang Chen, Deshanand Singh
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Patent number: 9147023Abstract: A method for designing a system on a target device is disclosed. A first netlist with a first set of functionally invariant boundaries (FIBs) is generated after performing extraction during synthesis of a first version of the system in a first compilation. One or more of the FIBs is invalidated from the first set after performing optimizations during synthesis in the first compilation resulting in a second netlist with a second set of FIBs. A third netlist with a third set of FIBs is generated after performing extraction during synthesis of a second version of the system having a changed portion in a second compilation. Connectivity of matching nodes from the first netlist and the third netlist reaching FIBs is traversed to identify equivalent nodes associated with identical regions. The identical region in the third netlist is replaced with an optimized synthesized region from the second netlist.Type: GrantFiled: March 28, 2014Date of Patent: September 29, 2015Assignee: Altera CorporationInventors: Doris Tzu Lang Chen, Deshanand Singh
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Patent number: 9134981Abstract: Systems and methods for increasing speed and reducing processing power of a compile process of programmable logic of an integrated circuit (IC) are provided. For example, in one embodiment, a method includes obtaining a high level program, comprising computer-readable instructions for implementation on programmable logic of an integrated circuit (IC); translating the high level program into low level code representative of functional components needed to execute functionalities of the high level program; generating a host program comprising computer-readable instructions for implementing the low level code based upon the high level program; obtaining modifications to the high level program; determining whether the modifications can be implemented by a new host program utilizing the low level code; and generating the new host program to implement the modifications, when the modifications can be implemented by the new host program utilizing the low level code.Type: GrantFiled: June 22, 2012Date of Patent: September 15, 2015Assignee: Altera CorporationInventors: Doris Tzu Lang Chen, Deshanand Singh
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Patent number: 9100012Abstract: Systems and methods for dynamically adjusting programs implemented on an integrated circuit (IC) are provided. During runtime, characteristics of the application may change or become known. Accordingly, the embodiments described herein allow for partial reconfiguration of kernels implemented on an IC during runtime to dynamically alter performance based upon these characteristics.Type: GrantFiled: December 14, 2012Date of Patent: August 4, 2015Assignee: Altera CorporationInventors: Doris Tzu Lang Chen, Deshanand Singh
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Publication number: 20150121321Abstract: A method of preparing a programmable integrated circuit device for configuration using a high-level language includes compiling a plurality of virtual programmable devices from descriptions in said high-level language. the compiling includes compiling configurations of configurable routing resources from programmable resources of said programmable integrated circuit device, and compiling configurations of a plurality of complex function blocks from programmable resources of said programmable integrated circuit device. A machine-readable data storage medium may be encoded with a library of such compiled configurations. A virtual programmable device may include a stall signal network and routing switches of the virtual programmable device may include stall signal inputs and outputs.Type: ApplicationFiled: January 6, 2015Publication date: April 30, 2015Inventors: Doris Tzu-Lang Chen, Deshanand Singh
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Patent number: 8959469Abstract: A method of preparing a programmable integrated circuit device for configuration using a high-level language includes compiling a plurality of virtual programmable devices from descriptions in said high-level language. The compiling includes compiling configurations of configurable routing resources from programmable resources of said programmable integrated circuit device, and compiling configurations of a plurality of complex function blocks from programmable resources of said programmable integrated circuit device. A machine-readable data storage medium may be encoded with a library of such compiled configurations. A virtual programmable device may include a stall signal network and routing switches of the virtual programmable device may include stall signal inputs and outputs.Type: GrantFiled: February 9, 2012Date of Patent: February 17, 2015Assignee: Altera CorporationInventors: Doris Tzu-Lang Chen, Deshanand Singh
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Patent number: 8732634Abstract: A method for designing a system on a target device is disclosed. A first netlist is generated or a first version of the system in a first compilation. Optimizations are performed on the first version of the system during synthesis resulting in a second netlist. A third netlist is generated or a second version of the system in a second compilation. The first version of the system in the first netlist and the second version of the system in the third netlist are differentiated to identify identical regions.Type: GrantFiled: June 3, 2013Date of Patent: May 20, 2014Assignee: Altera CorporationInventors: Doris Tzu Lang Chen, Deshanand Singh
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Patent number: 8650525Abstract: Systems and methods for increasing speed and reducing processing power of a compile process of programmable logic of an integrated circuit (IC) are provided. For example, in one embodiment, a method includes obtaining a high level program, comprising computer-readable instructions for implementation on programmable logic of an integrated circuit (IC); translating the high level program into low level code representative of functional components needed to execute functionalities of the high level program; generating a host program comprising computer-readable instructions for implementing the low level code based upon the high level program; obtaining modifications to the high level program; determining whether the modifications can be implemented by a new host program utilizing the low level code; and generating the new host program to implement the modifications, when the modifications can be implemented by the new host program utilizing the low level code.Type: GrantFiled: June 22, 2012Date of Patent: February 11, 2014Assignee: Altera CorporationInventors: Doris Tzu Lang Chen, Deshanand Singh
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Publication number: 20130346953Abstract: Systems and methods for increasing speed and reducing processing power of a compile process of programmable logic of an integrated circuit (IC) are provided. For example, in one embodiment, a method includes obtaining a high level program, comprising computer-readable instructions for implementation on programmable logic of an integrated circuit (IC); translating the high level program into low level code representative of functional components needed to execute functionalities of the high level program; generating a host program comprising computer-readable instructions for implementing the low level code based upon the high level program; obtaining modifications to the high level program; determining whether the modifications can be implemented by a new host program utilizing the low level code; and generating the new host program to implement the modifications, when the modifications can be implemented by the new host program utilizing the low level code.Type: ApplicationFiled: June 22, 2012Publication date: December 26, 2013Applicant: ALTERA CORPORATIONInventors: Doris Tzu Lang Chen, Deshanand Singh
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Publication number: 20130346925Abstract: Systems and methods for increasing speed and reducing processing power of a compile process of programmable logic of an integrated circuit (IC) are provided. For example, in one embodiment, a method includes obtaining a high level program, comprising computer-readable instructions for implementation on programmable logic of an integrated circuit (IC); translating the high level program into low level code representative of functional components needed to execute functionalities of the high level program; generating a host program comprising computer-readable instructions for implementing the low level code based upon the high level program; obtaining modifications to the high level program; determining whether the modifications can be implemented by a new host program utilizing the low level code; and generating the new host program to implement the modifications, when the modifications can be implemented by the new host program utilizing the low level code.Type: ApplicationFiled: June 22, 2012Publication date: December 26, 2013Applicant: ALTERA CORPORATIONInventors: Doris Tzu Lang Chen, Deshanand Singh
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Publication number: 20130212365Abstract: A method of preparing a programmable integrated circuit device for configuration using a high-level language includes compiling a plurality of virtual programmable devices from descriptions in said high-level language. The compiling includes compiling configurations of configurable routing resources from programmable resources of said programmable integrated circuit device, and compiling configurations of a plurality of complex function blocks from programmable resources of said programmable integrated circuit device. A machine-readable data storage medium may be encoded with a library of such compiled configurations. A virtual programmable device may include a stall signal network and routing switches of the virtual programmable device may include stall signal inputs and outputs.Type: ApplicationFiled: February 9, 2012Publication date: August 15, 2013Applicant: ALTERA CORPORATIONInventors: Doris Tzu-Lang Chen, Deshanand Singh
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Publication number: 20130212366Abstract: A method of configuring a programmable integrated circuit device uses a high-level language. The method includes compiling a plurality of virtual programmable devices from descriptions in the high-level language, describing a user configuration for the programmable integrated circuit device in the high-level language, parsing the user configuration using a programming processor, and selecting, as a result of that parsing, one of the compiled virtual programmable devices. That selected one of the compiled virtual programmable devices is instantiated on the programmable integrated circuit device, and the instantiated one of the compiled virtual programmable devices is configured with the user configuration.Type: ApplicationFiled: February 9, 2012Publication date: August 15, 2013Applicant: ALTERA CORPORATIONInventors: Doris Tzu-Lang Chen, Deshanand Singh