Patents by Inventor Doron Rajwan

Doron Rajwan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11899599
    Abstract: Systems, methods, and apparatuses relating to hardware control of processor performance levels are described. In one embodiment, a processor includes a plurality of logical processing elements; and a power management circuit to change a highest non-guaranteed performance level and a highest guaranteed performance level for each of the plurality of logical processing elements, and set a notification in a status register when the highest non-guaranteed performance level is changed to a new highest non-guaranteed performance level.
    Type: Grant
    Filed: November 16, 2021
    Date of Patent: February 13, 2024
    Assignee: INTEL CORPORATION
    Inventors: Eliezer Weissmann, Efraim Rotem, Doron Rajwan, Hisham Abu Salah, Ariel Gur, Guy M. Therien, Russell J. Fenger
  • Patent number: 11853140
    Abstract: Various techniques and circuit implementations for power reduction management in integrated circuits are disclosed. Specifically, a power manager circuit in an integrated circuit (e.g., a system on a chip) may modify power budgets for various components in the integrated circuit to reduce the amount of power control caused by external signaling that indicates a voltage regulator overload (e.g., a voltage droop).
    Type: Grant
    Filed: February 21, 2022
    Date of Patent: December 26, 2023
    Assignee: Apple Inc.
    Inventors: Doron Rajwan, Karl Daniel Wulcan, Tal Kuzi, Inder M. Sodhi, Achmed R. Zahir
  • Publication number: 20230393641
    Abstract: In one embodiment, a processor includes a plurality of cores, at least two of which may execute redundantly, a configuration register to store a first synchronization domain indicator to indicate that a first core and a second core are associated with a first synchronization domain, and a power controller having a synchronization circuit to cause a dynamic adjustment to a frequency of at least one of the first and second cores to cause these cores to operate at a common frequency, based at least in part on the first synchronization domain indicator. Other embodiments are described and claimed.
    Type: Application
    Filed: August 24, 2023
    Publication date: December 7, 2023
    Inventors: Efraim Rotem, Eliezer Weissmann, Doron Rajwan, Nir Rosenzweig, Yoni Aizik
  • Patent number: 11836026
    Abstract: A system includes multiple hardware circuits and protection circuitry. The multiple hardware circuits are coupled to respective power domains having respective sets of domain-specific power settings. The protection circuitry is configured to monitor requests in which one or more of the hardware circuits request transitions between the domain-specific power settings, to determine, from among multiple system-level combinations of the domain-specific power settings, a subset of system-level combinations that could potentially be traversed in performing the requested transitions, and to initiate a responsive action upon detecting that any of the system-level combinations in the subset is specified as invalid.
    Type: Grant
    Filed: February 17, 2022
    Date of Patent: December 5, 2023
    Assignee: APPLE INC.
    Inventors: Doron Rajwan, Ami Schwartzman, Lior Zimet
  • Patent number: 11836107
    Abstract: An electronic device includes circuitry and a plurality of ports. The plurality of ports includes an input port and an output port, configured to communicate data units with one or more other devices across a fabric of a System on a Chip (SoC), the data units include N data bits, N being an integer larger than 1. The circuitry is configured to receive an input data unit via the input port, to make a random decision of whether to invert the N data bits in the input data unit, to produce an output data unit by retaining or inverting the N data bits of the input data unit based on the random decision, and to send the output data unit via the output port.
    Type: Grant
    Filed: March 1, 2022
    Date of Patent: December 5, 2023
    Assignee: APPLE INC.
    Inventors: Doron Rajwan, Lior Zimet, Sagi Lahav
  • Patent number: 11822399
    Abstract: A temperature control apparatus is disclosed. An integrated circuit (IC) includes a plurality of temperature sensors, a first thermal control loop, and a second thermal control loop. The first thermal control loop is configured to control temperature of the IC by reducing a frequency of a clock signal provided to the IC in response to a temperature at one of the plurality of temperature sensors reaching a first temperature threshold. The second thermal control loop is configured to control temperature of the IC by dithering the clock signal provided to the IC in response to a temperature at one of the plurality of temperature sensors reaching a second temperature threshold that is greater than the first temperature threshold.
    Type: Grant
    Filed: July 28, 2021
    Date of Patent: November 21, 2023
    Assignee: Apple Inc.
    Inventors: Doron Rajwan, Tal Kuzi, Keith Cox, Yizhang Yang
  • Patent number: 11822409
    Abstract: In an embodiment, a processor includes a core domain with a plurality of cores and a power controller having a first logic to receive a first request to increase an operating voltage of a first core of the core domain to a second voltage, to instruct a voltage regulator to increase the operating voltage to an interim voltage, and to thereafter instruct the voltage regulator to increase the operating voltage to the second voltage. Other embodiments are described and claimed.
    Type: Grant
    Filed: November 1, 2022
    Date of Patent: November 21, 2023
    Assignee: Daedauls Prime LLC
    Inventors: Ryan D. Wells, Itai Feit, Doron Rajwan, Nadav Shulman, Zeev Offen, Inder M. Sodhi
  • Patent number: 11822411
    Abstract: Systems, apparatuses, and methods for implementing telemetry push aggregation techniques are described. A computing system includes one or more input/output (I/O) agents interposed between functional units and a communication fabric. A given I/O agent receives a set of aggregation rules from a power management unit. The I/O agent monitors traffic from the functional units, and the I/O agent generates telemetry data from the traffic data based on the set of aggregation rules. The telemetry data is used by the power management unit to make adjustments to one or more power settings.
    Type: Grant
    Filed: May 6, 2021
    Date of Patent: November 21, 2023
    Assignee: Apple Inc.
    Inventors: Doron Rajwan, Karl Daniel Wulcan, Lital Levy-Rubin, Tal Kuzi
  • Patent number: 11815979
    Abstract: Embodiments include apparatuses, methods, and systems including a power control unit to control different power consumptions by one or more processors to operate different applications. The power control unit may receive power information that may include a priority information for each application to be operated on the one or more processors, determine to control, based on the power information for different applications, different power consumptions by the one or more processors to operate the different applications. Other embodiments may also be described and claimed.
    Type: Grant
    Filed: August 22, 2017
    Date of Patent: November 14, 2023
    Assignee: Intel Corporation
    Inventors: Efraim Rotem, Eliezer Weissmann, Doron Rajwan, Yoni Aizik, Esfir Natanzon, Nir Rosenzweig, Nadav Shulman, Bart Plackle
  • Publication number: 20230280772
    Abstract: An apparatus includes hardware circuits, a front-end power supply, voltage regulators, and control circuitry. The front-end power supply generates electrical power for the hardware circuits. The front-end power supply includes power stages that generate portions of electrical power and are activated and deactivated independently. The voltage regulators are connected to an output of the front-end power supply and provide adjustable operating voltages to the hardware circuits.
    Type: Application
    Filed: May 10, 2023
    Publication date: September 7, 2023
    Inventors: Doron Rajwan, Craig S Forbell, Jamie L. Langlinais
  • Publication number: 20230281154
    Abstract: An electronic device includes circuitry and a plurality of ports. The plurality of ports includes an input port and an output port, configured to communicate data units with one or more other devices across a fabric of a System on a Chip (SoC), the data units include N data bits, N being an integer larger than 1. The circuitry is configured to receive an input data unit via the input port, to make a random decision of whether to invert the N data bits in the input data unit, to produce an output data unit by retaining or inverting the N data bits of the input data unit based on the random decision, and to send the output data unit via the output port.
    Type: Application
    Filed: March 1, 2022
    Publication date: September 7, 2023
    Inventors: Doron Rajwan, Lior Zimet, Sagi Lahav
  • Patent number: 11740682
    Abstract: A processor includes a plurality of cores, at least two of which may execute redundantly, a configuration register to store a first synchronization domain indicator to indicate that a first core and a second core are associated with a first synchronization domain, and a power controller having a synchronization circuit to cause a dynamic adjustment to a frequency of at least one of the first and second cores to cause these cores to operate at a common frequency, based at least in part on the first synchronization domain indicator.
    Type: Grant
    Filed: May 26, 2022
    Date of Patent: August 29, 2023
    Assignee: Intel Corporation
    Inventors: Efraim Rotem, Eliezer Weissmann, Doron Rajwan, Nir Rosenzweig, Yoni Aizik
  • Publication number: 20230259189
    Abstract: A system includes multiple hardware circuits and protection circuitry. The multiple hardware circuits are coupled to respective power domains having respective sets of domain-specific power settings. The protection circuitry is configured to monitor requests in which one or more of the hardware circuits request transitions between the domain-specific power settings, to determine, from among multiple system-level combinations of the domain-specific power settings, a subset of system-level combinations that could potentially be traversed in performing the requested transitions, and to initiate a responsive action upon detecting that any of the system-level combinations in the subset is specified as invalid.
    Type: Application
    Filed: February 17, 2022
    Publication date: August 17, 2023
    Inventors: Doron Rajwan, Ami Schwartzman, Lior Zimet
  • Patent number: 11709512
    Abstract: An apparatus includes hardware circuits, a front-end power supply, voltage regulators, and control circuitry. The front-end power supply generates electrical power for the hardware circuits. The front-end power supply includes power stages that generate portions of electrical power and are activated and deactivated independently. The voltage regulators are connected to an output of the front-end power supply and provide adjustable operating voltages to the hardware circuits.
    Type: Grant
    Filed: January 11, 2022
    Date of Patent: July 25, 2023
    Assignee: APPLE INC.
    Inventors: Doron Rajwan, Craig S Forbell, Jamie L Langlinais
  • Patent number: 11693472
    Abstract: Various techniques and circuit implementations for power reduction management in integrated circuits are disclosed. Certain techniques include the implementation of rate control circuits to control a clock rate for circuits associated with a communication fabric in an integrated circuit. The clock rate may be reduced based trigger signals received from power delivery trigger circuits coupled to the integrated circuit and voltage regulators providing power to the integrated circuit. Additional techniques may include the use of rate limiter circuits in a memory pipeline.
    Type: Grant
    Filed: February 21, 2022
    Date of Patent: July 4, 2023
    Assignee: Apple Inc.
    Inventors: Ilya Granovsky, Doron Rajwan, Tal Kuzi, Nir Leshem, Lior Zimet
  • Patent number: 11687139
    Abstract: Methods and apparatus relating to multi-level CPU (Central Processing Unit) high current protection are described. In one embodiment, different workloads may be assigned different license types and/or weights based on micro-architectural events (such as uop (micro-operation) types and sizes) and/or data types. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: March 28, 2022
    Date of Patent: June 27, 2023
    Assignee: Intel Corporation
    Inventors: Efraim Rotem, Nir Rosenzweig, Doron Rajwan, Alon Naveh, Eliezer Weissmann
  • Publication number: 20230168732
    Abstract: In one embodiment, a processor includes at least one core to execute instructions and a power controller coupled to the at least one core. The power controller may include a first logic to cause the at least one core to exit an idle state and enter into a maximum performance state for a first time duration, thereafter enter into an intermediate power state for a second time duration, and thereafter enter into a sustained performance state. Other embodiments are described and claimed.
    Type: Application
    Filed: August 4, 2022
    Publication date: June 1, 2023
    Applicant: Tahoe Research, Ltd.
    Inventors: Efraim Rotem, Doron Rajwan, Eliezer Weissmann, Nir Rosenzweig, Eric Distefano, Ishmael F. Santos, James G. Hermerding, II
  • Publication number: 20230109984
    Abstract: In an embodiment, a system may include a plurality of component circuits. The plurality of component circuits may include rate control circuits the control power consumption in the component circuits based on indications of power allocated to the component circuits. In an embodiment, the rate control circuits may transmit power requests for the component circuits and a floor request representing a minimum amount of power that may ensure reliable operation.
    Type: Application
    Filed: January 11, 2022
    Publication date: April 13, 2023
    Inventors: Doron Rajwan, Inder M. Sodhi, Keith Cox, Jung Wook Cho, Kevin I. Park, Tal Kuzi
  • Publication number: 20230101217
    Abstract: In an embodiment, a system may include a plurality of component circuits. The plurality of component circuits may include rate control circuits the control power consumption in the component circuits based on indications of power allocated to the component circuits. In an embodiment, the rate control circuits may transmit power requests for the component circuits and a floor request representing a minimum amount of power that may ensure reliable operation.
    Type: Application
    Filed: January 11, 2022
    Publication date: March 30, 2023
    Inventors: Doron Rajwan, Inder M. Sodhi, Keith Cox, Jung Wook Cho, Kevin I. Park, Tal Kuzi
  • Publication number: 20230077747
    Abstract: An apparatus includes hardware circuits, a front-end power supply, voltage regulators, and control circuitry. The front-end power supply generates electrical power for the hardware circuits. The front-end power supply includes power stages that generate portions of electrical power and are activated and deactivated independently. The voltage regulators are connected to an output of the front-end power supply and provide adjustable operating voltages to the hardware circuits.
    Type: Application
    Filed: January 11, 2022
    Publication date: March 16, 2023
    Inventors: Doron Rajwan, Craig S Forbell, Jamie L Langlinais