Abstract: Apparatus for storing and retrieving display information in the memory of a video display terminal is disclosed. Terminal processor logical addresses are mapped into terminal memory in both a pixel address format and a word address format. Terminal memory is divided into four planes, each plane containing one bit of the 4-bit ordinal associated with each pixel in the color display image. Address interface logic generates the appropriate RAM row and column addresses based on the type of memory access and the purpose of the access. A plurality of separate write enable signals, separate upper and lower column address strobe signals and separate row address strobes for each plane allow flexibility in placing data in or removing data from terminal memory planes.

Abstract: Apparatus and method for generating monitor synchronization signals in a terminal capable of operating at either a 31.5 Khz or 15.75 Khz horizontal video scan rate is disclosed. A first set of counters count incremental locations along each horizontal scan line. The outputs of these counters are provided to a memory which provides a blanking signal and three synchronization signals. The memory also provides a clocking input to a second set of counters which count horizontal scan lines. These second counters are preloaded to values which depend on the scan mode selected, the frame being displayed, the refresh rate and whether a vertical video or vertical blanking operation is underway. A second memory receives the outputs of the second counter set, the frame being displayed and the refresh rate signal and provides selection inputs used to choose the signals to be provided as the composite blanking and composite monitor synchronization signals.