Patents by Inventor Douglas A. Laird

Douglas A. Laird has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10992648
    Abstract: Methods and apparatus for a Secure Time Communication System (10) are disclosed. One embodiment of the invention provides secure and non-interactive communication of clock information over an unsecured communications channel. This communication provides perfect forward secrecy, while detecting and blocking message spoofing, message replay, denial of service and cryptographic performance attacks. This mechanism also bounds the effect of message delay manipulation. The mechanism consists of two components, a filtered time encryptor (16) and a filtered time decryptor (28). The filtered time encryptor (16) produces a message in two parts; a time token followed by an encrypted message body. The time token is used as a filter to detect most attacks and to determine the message key.
    Type: Grant
    Filed: February 16, 2017
    Date of Patent: April 27, 2021
    Assignee: Blue Armor Technologies, LLC
    Inventors: John William Hayes, Douglas A. Laird, Charles Andrew Gram
  • Publication number: 20140100215
    Abstract: The invention provides methods of treating cancer with a combination of compounds which inhibit kinases, more specifically MEK and PI3K.
    Type: Application
    Filed: December 7, 2013
    Publication date: April 10, 2014
    Applicant: Exelixis, Inc.
    Inventors: Dana T. Aftab, A. Douglas Laird, Peter Lamb, Jean-Francois A. Martini
  • Patent number: 8642584
    Abstract: The invention provides methods of treating cancer with a combination of compounds which inhibit kinases, more specifically MEK and PI3K.
    Type: Grant
    Filed: August 7, 2012
    Date of Patent: February 4, 2014
    Assignee: Exelixis, Inc.
    Inventors: Dana T. Aftab, A. Douglas Laird, Peter Lamb, Jean-Francois A. Martini
  • Publication number: 20120302545
    Abstract: The invention provides methods of treating cancer with a combination of compounds which inhibit kinases, more specifically MEK and PI3K.
    Type: Application
    Filed: August 7, 2012
    Publication date: November 29, 2012
    Applicant: Exelixis, Inc.
    Inventors: Dana T. Aftab, A. Douglas Laird, Peter Lamb, Jean-Francois A. Martini
  • Publication number: 20100075947
    Abstract: The invention provides methods of treating cancer with a combination of compounds which inhibit kinases, more specifically MEK and PI3K.
    Type: Application
    Filed: August 16, 2007
    Publication date: March 25, 2010
    Applicant: EXELIXIS, INC.
    Inventors: Dana T. Aftab, A. Douglas Laird, Peter Lamb, Jean-Francois A. Martini
  • Patent number: 7557605
    Abstract: A system including a plurality of programmable logic blocks, a plurality of special-purpose blocks, and a configurable high-speed mesh interconnect fabric operatively connecting the plurality of programmable logic blocks and the plurality of special-purpose blocks, where the configurable high-speed mesh interconnect fabric is configured to implement a plurality of interconnect pipeline buses spanning across the system.
    Type: Grant
    Filed: September 14, 2007
    Date of Patent: July 7, 2009
    Assignee: Cswitch Corporation
    Inventors: Godfrey P. D'Souza, Douglas Laird, Malcolm J. Wing, Colin N. Murphy, Dana L. How, Robert Yu, Jay B. Patel, Ivo Dobbelaere, Jason Golbus, Suresh Subramaniam, Mukunda Krishnappa, Pohrong R. Chu, Dave Trossen, Kevin James
  • Publication number: 20090072858
    Abstract: A system including a plurality of programmable logic blocks, a plurality of special-purpose blocks, and a configurable high-speed mesh interconnect fabric operatively connecting the plurality of programmable logic blocks and the plurality of special-purpose blocks, where the configurable high-speed mesh interconnect fabric is configured to implement a plurality of interconnect pipeline buses spanning across the system.
    Type: Application
    Filed: September 14, 2007
    Publication date: March 19, 2009
    Applicant: CSWITCH CORPORATION
    Inventors: Godfrey P. D'Souza, Douglas Laird, Malcolm J. Wing, Colin N. Murphy, Dana L. How, Robert Yu, Jay B. Patel, Ivo Dobbelaere, Jason Golbus, Suresh Subramaniam, Mukunda Krishnappa, Pohrong R. Chu, Dave Trossen, Kevin James
  • Patent number: 6031992
    Abstract: A microprocessor for a host computer designed to execute target application programs for a target computer having a target instruction set including the combination of code morphing software, and morph host processing hardware designed to execute instructions of a host instruction set, the combination of the code morphing software and the morph host processing hardware comprising means to translate a set of target instructions into instructions of a host instruction set, means to optimize the instructions of the host instruction set translated from the target application program speculating upon the occurrence of a condition, means to determine under control of the code morphing software official state of the target computer which existed at the beginning of a translation of a set of target instructions during execution of the target application program by the microprocessor, means for updating state of the target computer from state of the host computer when a set of host instructions executes in accordance
    Type: Grant
    Filed: July 5, 1996
    Date of Patent: February 29, 2000
    Assignee: Transmeta Corporation
    Inventors: Robert F. Cmelik, David R. Ditzel, Edmund J. Kelly, Colin B. Hunter, Douglas A. Laird, Malcolm John Wing, Grzegorz B. Zyner
  • Patent number: 5606270
    Abstract: A dynamic clocked inverter latch with reduced charge leakage includes a first node biasing circuit with a P-MOSFET and an N-MOSFET totem-pole-coupled between VDD and an output node, and a second node biasing circuit with another N-MOSFET and another P-MOSFET totem-pole-coupled between the output node and VSS. The first P-MOSFET receives an input data signal and the first N-MOSFET receives a clock signal and in accordance therewith together cause the output node to charge to a charged state having a charge voltage associated therewith. The second N-MOSFET also receives the input data signal while the second P-MOSFET receives the inverse of the clock signal and in accordance therewith together cause the output node to discharge to a discharged state having a discharge voltage associated therewith.
    Type: Grant
    Filed: December 16, 1994
    Date of Patent: February 25, 1997
    Assignee: Sun Microsystems, Inc.
    Inventors: Godfrey P. D'Souza, James F. Testa, Douglas A. Laird, James B. Burr
  • Patent number: 5546022
    Abstract: A static logic circuit with improved output signal levels includes a static complementary MOSFET circuit with a signal node and pull-up and pull-down amplifiers, each with at least one biasing circuit, connected thereto. The pull-up and pull-down amplifiers are connected to VDD and VSS, respectively, and receive one or more logic signals (e.g. one for an inverter and more for logic gates such as AND, OR, etc.) and one or more bias signals and in accordance therewith provide pull-up and pull-down voltages, respectively, to the signal node. In accordance with the applied pull-up or pull-down voltage, the signal node charges to a charge state with an associated node voltage approximately equal to VDD or VSS, respectively. Each biasing circuit receives the same input logic signal as its associated pull-up or pull-down amplifier and provides thereto a bias signal approximately equal to VSS or VDD, respectively.
    Type: Grant
    Filed: December 16, 1994
    Date of Patent: August 13, 1996
    Assignee: Sun Microsystems, Inc.
    Inventors: Godfrey P. D'Souza, Douglas A. Laird
  • Patent number: 5444296
    Abstract: A package and packaging technique for enhancing performance of critical chips within an electronic device, wherein the critical chips comprise an integrated circuit. The package includes a main package incorporating a first integrated circuit coupled to a substrate board. At least one package having a second integrated circuit is mounted to the main package in order to reduce (i) propagation delay for data to transfer between critical chips within the main package and one of the plurality of packages or between the critical chips within the plurality of packages and (ii) total footprint area. The method for implementing such a package including the steps of packaging the first and second integrated circuits and electrically coupling these integrating circuits together in a mounted position.
    Type: Grant
    Filed: November 22, 1993
    Date of Patent: August 22, 1995
    Assignee: Sun Microsystems, Inc.
    Inventors: Sunil Kaul, Douglas A. Laird
  • Patent number: 5180937
    Abstract: A delay compensator circuit is disclosed to compensate for variations in temperature, supply voltage and process. A monitor circuit is further disclosed that allows the monitoring of the delay of a delay element. The delay compensator circuit and monitor circuit lend themselves easily to the ASIC design methodology since they use conventional ASIC building blocks; namely gates, memory elements and delay elements. The delay compensator and monitor use a time base to track variations in circuit parameters by monitoring the delay through a delay element (delay line or sub-circuit). Compensation may be achieved by switching delays in or out of the circuit to be compensated based on variations of temperature, voltage, and process as measured using the time base. The delay compensator permits the designer to control the output hold time independently of the output delay time. The delay compensator enables a latching device to hold the output signal for the required duration after a reference.
    Type: Grant
    Filed: February 28, 1992
    Date of Patent: January 19, 1993
    Assignee: LSI Logic Corporation
    Inventors: Douglas Laird, Godfrey P. D'Souza
  • Patent number: 5058110
    Abstract: A computer network method and apparatus. The present invention comprises a computer network having one or more hubs, each hub comprising one or more connection means for connection of computing devices to the network. Each connection means comprising a first interface means for coupling with a computing device, a second interface means for coupling with the network and a protocol processing means. The protocol processing means receives message packets and, depending on the message type, processing the message as either a network control message or a data transfer message. The present invention provides for "flow through" of data in the case of data transfer messages. The present invention further provides for calculation of checksum bytes as a data packet is received by the protocol processing means.
    Type: Grant
    Filed: May 3, 1989
    Date of Patent: October 15, 1991
    Assignee: Ultra Network Technologies
    Inventors: Robert Beach, Mark Bryers, Casey Cox, Richard Fall, Norman Finn, Douglas Laird