Patents by Inventor Douglas Dean Lopata
Douglas Dean Lopata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10020739Abstract: An integrated current replicator includes a first current sense resistor configured to sense a first input current to a power converter during a primary portion of a duty cycle and a first transconductance amplifier configured produce a first voltage at a common circuit node proportional to the first input current during the primary portion of the duty cycle. The integrated current replicator includes a second current sense resistor configured to sense a second input current to the power converter during a complementary portion of the duty cycle and a second transconductance amplifier configured produce a second voltage at the common circuit node proportional to the second input current during the complementary portion of the duty cycle. The integrated current replicator includes an amplifier configured to produce a voltage replicating the first input current and the second input current from the first voltage and the second voltage.Type: GrantFiled: March 27, 2014Date of Patent: July 10, 2018Assignee: Altera CorporationInventors: Douglas Dean Lopata, Jeffrey Demski, Jay Norton, Miguel Rojas-Gonzalez
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Patent number: 9673135Abstract: A semiconductor device having substantially minor-symmetric terminals and methods of forming the same. In one embodiment, the semiconductor device includes a semiconductor switch having a control node and a switched node, the switched node being coupled to first and second output terminals of the semiconductor device, the first and second output terminals being positioned in a substantially minor-symmetric arrangement on the semiconductor device. The semiconductor device also includes a control element having first and second input nodes and an output node, the first and second input nodes being coupled to first and second input terminals, respectively, of the semiconductor device and the output node being coupled to the control node of the semiconductor switch, the first and second input terminals being substantially center-positioned on the semiconductor device.Type: GrantFiled: January 13, 2014Date of Patent: June 6, 2017Assignee: Altera CorporationInventors: John D. Weld, Douglas Dean Lopata, Wei Zhang
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Patent number: 9673192Abstract: A semiconductor device including a resistor metallic layer and method forming the same. In one embodiment, the semiconductor device includes a source region and a drain region of a power switch on a substrate. The semiconductor device also includes the resistor metallic layer over the source region and the drain region of the power switch. The resistor metallic layer includes a current sense resistor including a first current sense resistor metallic strip coupled between a first cross member and a second cross member, and a first gain resistor including a first gain resistor metallic strip coupled to the first cross member. The semiconductor device also includes an amplifier over the substrate and coupled to the first gain resistor metallic strip.Type: GrantFiled: March 27, 2015Date of Patent: June 6, 2017Assignee: Altera CorporationInventors: Douglas Dean Lopata, Jeffrey Demski, Jay Norton, Miguel Rojas-Gonzales
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Patent number: 9627028Abstract: An apparatus including a memory module and power converter and method of operating the same. In one embodiment, the apparatus includes a memory module, located on a circuit board, configured to operate from a first voltage and a second voltage being a multiple of the first voltage. The apparatus also includes a power converter employing a switched-capacitor power train, located on the circuit board, configured to provide the second voltage for the memory module from the first voltage.Type: GrantFiled: September 2, 2014Date of Patent: April 18, 2017Assignee: Enpirion, Inc.Inventors: Narciso Mera, Douglas Dean Lopata, Ashraf W. Lotfi
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Patent number: 9553081Abstract: A semiconductor device and method of forming the same including, in one embodiment, a semiconductor die formed with a plurality of laterally diffused metal oxide semiconductor (“LDMOS”) cells. The semiconductor device also includes a redistribution layer electrically coupled to the plurality of LDMOS cells and a plurality of metallic pillars distributed over and electrically coupled to the redistribution layer.Type: GrantFiled: November 27, 2013Date of Patent: January 24, 2017Assignee: Enpirion, Inc.Inventors: Ashraf W. Lotfi, Jeffrey Demski, Anatoly Feygenson, Douglas Dean Lopata, Jay Norton, John D. Weld
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Patent number: 9536938Abstract: A semiconductor device including a resistor metallic layer and method forming the same. In one embodiment, the semiconductor device includes a source region and a drain region of a semiconductor switch on a substrate. The semiconductor device also includes the resistor metallic layer over the source region and the drain region of the semiconductor switch. The resistor metallic layer includes a first resistor with a first resistor metallic strip coupled between a first cross member and a second cross member of the resistor metallic layer.Type: GrantFiled: March 27, 2015Date of Patent: January 3, 2017Assignee: Altera CorporationInventors: Douglas Dean Lopata, Jeffrey Demski, Jay Norton, Miguel Rojas-Gonzales
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Patent number: 9508785Abstract: A semiconductor device including a resistor metallic layer and method forming the same. In one embodiment, the semiconductor device includes a source region and a drain region of a semiconductor switch on a substrate. The semiconductor device also includes the resistor metallic layer over the source region and the drain region of the semiconductor switch. The resistor metallic layer includes a first resistor with a first resistor metallic strip coupled between a first cross member and a second cross member of the resistor metallic layer.Type: GrantFiled: March 27, 2015Date of Patent: November 29, 2016Assignee: Altera CorporationInventors: Douglas Dean Lopata, Jeffrey Demski, Jay Norton, Miguel Rojas-Gonzales
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Patent number: 9443839Abstract: A semiconductor device and method of forming the same including, in one embodiment, a semiconductor die formed with a plurality of laterally diffused metal oxide semiconductor (“LDMOS”) cells, and a metallic layer electrically coupled to the plurality of LDMOS cells. The semiconductor device also includes a plurality of gate drivers positioned along a periphery of the semiconductor die and electrically coupled to gates of the plurality of LDMOS cells through the metallic layer.Type: GrantFiled: November 27, 2013Date of Patent: September 13, 2016Assignee: Enpirion, Inc.Inventors: Ashraf W. Lotfi, Jeffrey Demski, Anatoly Feygenson, Douglas Dean Lopata, Jay Norton, John D. Weld
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Patent number: 9299691Abstract: A semiconductor device and method of forming the same including, in one embodiment, a substrate and a plurality of source and drain regions formed as alternating pattern on the substrate. The semiconductor device also includes a plurality of gates formed over the substrate between and parallel to ones of the plurality of source and drain regions. The semiconductor device also includes a first plurality of alternating source and drain metallic strips formed in a first metallic layer above the substrate and parallel to and forming an electrical contact with respective ones of the plurality of source and drain regions.Type: GrantFiled: November 27, 2013Date of Patent: March 29, 2016Assignee: Enpirion, Inc.Inventors: Ashraf W. Lotfi, Jeffrey Demski, Anatoly Feygenson, Douglas Dean Lopata, Jay Norton, John D. Weld
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Patent number: 9246390Abstract: A power converter and method of controlling the same for selected modes of operation. In one embodiment, the power converter includes a first power switch coupled to a source of electrical power and a second power switch coupled to the first power switch and to an output terminal of the power converter. The power converter also includes a controller configured to control an operation of the first and second power switches during selected modes of operation.Type: GrantFiled: November 4, 2010Date of Patent: January 26, 2016Assignee: Enpirion, Inc.Inventors: Douglas Dean Lopata, Ashraf W. Lotfi
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Publication number: 20150280558Abstract: An integrated current replicator includes a first current sense resistor configured to sense a first input current to a power converter during a primary portion of a duty cycle and a first transconductance amplifier configured produce a first voltage at a common circuit node proportional to the first input current during the primary portion of the duty cycle. The integrated current replicator includes a second current sense resistor configured to sense a second input current to the power converter during a complementary portion of the duty cycle and a second transconductance amplifier configured produce a second voltage at the common circuit node proportional to the second input current during the complementary portion of the duty cycle. The integrated current replicator includes an amplifier configured to produce a voltage replicating the first input current and the second input current from the first voltage and the second voltage.Type: ApplicationFiled: March 27, 2014Publication date: October 1, 2015Applicant: ALTERA CORPORATIONInventors: Douglas Dean Lopata, Jeffrey Demski, Jay Norton, Miguel Rojas-Gonzalez
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Publication number: 20150200155Abstract: A semiconductor device having substantially minor-symmetric terminals and methods of forming the same. In one embodiment, the semiconductor device includes a semiconductor switch having a control node and a switched node, the switched node being coupled to first and second output terminals of the semiconductor device, the first and second output terminals being positioned in a substantially minor-symmetric arrangement on the semiconductor device. The semiconductor device also includes a control element having first and second input nodes and an output node, the first and second input nodes being coupled to first and second input terminals, respectively, of the semiconductor device and the output node being coupled to the control node of the semiconductor switch, the first and second input terminals being substantially center-positioned on the semiconductor device.Type: ApplicationFiled: January 13, 2014Publication date: July 16, 2015Applicant: Altera CorporationInventors: John D. Weld, Douglas Dean Lopata, Wei Zhang
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Publication number: 20150200156Abstract: A module having substantially mirror-symmetric terminals and methods of forming the same. In one embodiment, the module has first and second module terminals and includes a first semiconductor device with first and second terminals in a substantially mirror-symmetric arrangement on the first semiconductor device and coupled to a first common node of the first semiconductor device. The module also includes a second semiconductor device including third and fourth terminals in a substantially mirror-symmetric arrangement on the second semiconductor device and coupled to a second common node of the second semiconductor device. At least one of the first and second terminals is coupled to the first module terminal, and at least one of the third and fourth terminals are coupled to the second module terminal. The first and second module terminals are in a substantially mirror-symmetric arrangement on the module.Type: ApplicationFiled: January 13, 2014Publication date: July 16, 2015Applicant: ALTERA CORPORATIONInventors: John D. Weld, Douglas Dean Lopata, Wei Zhang
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Patent number: 9054086Abstract: A module having a discrete passive element and a semiconductor device, and method of forming the same. In one embodiment, the module includes a patterned leadframe, a discrete passive element mounted on an upper surface of the leadframe, and a thermally conductive, electrically insulating material formed on an upper surface of the discrete passive element. The module also includes a semiconductor device bonded to an upper surface of the thermally conductive, electrically insulating material.Type: GrantFiled: October 2, 2008Date of Patent: June 9, 2015Assignee: Enpirion, Inc.Inventors: Ashraf W. Lotfi, Douglas Dean Lopata, John David Weld, Mathew A. Wilkowski
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Publication number: 20140369147Abstract: An apparatus including a memory module and power converter and method of operating the same. In one embodiment, the apparatus includes a memory module, located on a circuit board, configured to operate from a first voltage and a second voltage being a multiple of the first voltage. The apparatus also includes a power converter employing a switched-capacitor power train, located on the circuit board, configured to provide the second voltage for the memory module from the first voltage.Type: ApplicationFiled: September 2, 2014Publication date: December 18, 2014Applicant: ENPIRION, INC.Inventors: Narciso Mera, Douglas Dean Lopata, Ashraf W. Lotfi
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Patent number: 8867295Abstract: An apparatus including a memory module and power converter and method of operating the same. In one embodiment, the apparatus includes a memory module, located on a circuit board, configured to operate from a first voltage and a second voltage being a multiple of the first voltage. The apparatus also includes a power converter employing a switched-capacitor power train, located on the circuit board, configured to provide the second voltage for the memory module from the first voltage.Type: GrantFiled: April 18, 2011Date of Patent: October 21, 2014Assignee: Enpirion, Inc.Inventors: Narciso Mera, Douglas Dean Lopata, Ashraf W. Lotfi
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Publication number: 20140159130Abstract: An apparatus and method of forming the same including, in one embodiment, a printed circuit board and a semiconductor device coupled to the printed circuit board. The apparatus also includes a decoupling device coupled to the printed circuit board and positioned under the semiconductor device.Type: ApplicationFiled: November 27, 2013Publication date: June 12, 2014Applicant: Enpirion, Inc.Inventors: Ashraf W. Lotfi, Jeffrey Demski, Anatoly Feygenson, Douglas Dean Lopata, Jay Norton, John D. Weld
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Publication number: 20140151794Abstract: A semiconductor device and method of forming the same including, in one embodiment, a semiconductor die formed with a plurality of laterally diffused metal oxide semiconductor (“LDMOS”) cells. The semiconductor device also includes a redistribution layer electrically coupled to the plurality of LDMOS cells and a plurality of metallic pillars distributed over and electrically coupled to the redistribution layer.Type: ApplicationFiled: November 27, 2013Publication date: June 5, 2014Applicant: Enpirion, Inc.Inventors: Ashraf W. Lotfi, Jeffrey Demski, Anatoly Feygenson, Douglas Dean Lopata, Jay Norton, John D. Weld
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Publication number: 20140151797Abstract: A semiconductor device and method of forming the same including, in one embodiment, a substrate and a plurality of source and drain regions formed as alternating pattern on the substrate. The semiconductor device also includes a plurality of gates formed over the substrate between and parallel to ones of the plurality of source and drain regions. The semiconductor device also includes a first plurality of alternating source and drain metallic strips formed in a first metallic layer above the substrate and parallel to and forming an electrical contact with respective ones of the plurality of source and drain regions.Type: ApplicationFiled: November 27, 2013Publication date: June 5, 2014Applicant: Enpirion, Inc.Inventors: Ashraf W. Lotfi, Jeffrey Demski, Anatoly Feygenson, Douglas Dean Lopata, Jay Norton, John D. Weld
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Publication number: 20140151795Abstract: A semiconductor device and method of forming the same including, in one embodiment, a semiconductor die formed with a plurality of laterally diffused metal oxide semiconductor (“LDMOS”) cells, and a metallic layer electrically coupled to the plurality of LDMOS cells. The semiconductor device also includes a plurality of gate drivers positioned along a periphery of the semiconductor die and electrically coupled to gates of the plurality of LDMOS cells through the metallic layer.Type: ApplicationFiled: November 27, 2013Publication date: June 5, 2014Applicant: Enpirion, Inc.Inventors: Ashraf W. Lotfi, Jeffrey Demski, Anatoly Feygenson, Douglas Dean Lopata, Jay Norton, John D. Weld