Abstract: An apparatus is provided that improves memory storage and access speed by repackaging various types of memories, SRAM, DRAM, and Disk, into a single storage unit. Each unit contains a slice of all the various memories along with programmable logic to control the accessing of the memories. This unit appears to the central processing unit (CPU) of a computer system as an extremely large secondary cache. Independent management of each unit greatly reduces bus traffic to implement any particular address space. By using a plurality of these memory units, an extremely large amount of memory can be accessed by the CPU with the speed of accessing a cache system.

Abstract: A transaction card having in it a semiconductor microcomputer with data storing capability is inserted into a receptor having circuitry for interacting with the microcomputer. Operating power and a clock signal for the microcomputer are transferred from the receptor to the card via an inductive coupling between a coil and magnetic core in the receptor and a coil and ferromagnetic member constituting a flexible wafer inductive device ("FWID") in the card. For purposes of data transfer between the card and receptor, the card includes two additional FWIDS which, when the card is in the receptor, are inductively coupled with corresponding coils in the receptor. One of such additional FWIDS is used to transfer data from the microcomputer in the card to a microcomputer in the receptor, while the other additional FWID is used for data transfer in the opposite direction between these two microcomputers.