Patents by Inventor Douglas M. Bishop
Douglas M. Bishop has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11832534Abstract: Methods of forming variable-resistance devices include forming a variable-resistance layer between a first terminal and a second terminal from a material that varies in resistance based on an oxygen concentration. An electrolyte layer is formed over the variable-resistance layer from a material that is stable at room temperature and that conducts oxygen ions in accordance with an applied voltage. A conductive gate layer is formed over the electrolyte layer.Type: GrantFiled: December 23, 2020Date of Patent: November 28, 2023Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Teodor K Todorov, Douglas M. Bishop, Jianshi Tang, John Rozen
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Publication number: 20230210027Abstract: A method of fabricating a synaptic device is provided. The method includes forming a channel layer between a first terminal and a second terminal. The channel layer varies in resistance based on a magnesium concentration in the channel layer. The method further includes forming an electrolyte layer. The electrolyte layer includes a magnesium ion conductive material. A third terminal is formed over the electrolyte layer and applies a signal to the electrolyte layer and the channel layer.Type: ApplicationFiled: March 6, 2023Publication date: June 29, 2023Inventors: Douglas M. Bishop, Martin Michael Frank, Teodor Krassimirov Todorov
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Patent number: 11690304Abstract: A method of fabricating a synaptic device is provided. The method includes forming a channel layer between a first terminal and a second terminal. The channel layer varies in resistance based on a magnesium concentration in the channel layer. The method further includes forming an electrolyte layer. The electrolyte layer includes a magnesium ion conductive material. A third terminal is formed over the electrolyte layer and applies a signal to the electrolyte layer and the channel layer.Type: GrantFiled: October 7, 2021Date of Patent: June 27, 2023Assignee: International Business Machines CorporationInventors: Douglas M. Bishop, Martin Michael Frank, Teodor Krassimirov Todorov
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Patent number: 11586899Abstract: A method of fabricating a neuromorphic device includes forming a variable-resistance layer between a first terminal and a second terminal, the variable-resistance layer varies in resistance based on an oxygen concentration in the variable-resistance layer. The method further includes forming an electrolyte layer over the variable-resistance layer that is stable at room temperature and that conducts oxygen ions in accordance with an applied voltage. The method further includes forming a gate layer over the electrolyte layer to apply a voltage on the electrolyte layer and the variable-resistance layer, the gate layer formed using an oxygen scavenging material.Type: GrantFiled: June 10, 2019Date of Patent: February 21, 2023Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Teodor Krassimirov Todorov, Jianshi Tang, Douglas M. Bishop, John Rozen, Takashi Ando
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Patent number: 11557690Abstract: Semitransparent chalcogen solar cells and techniques for fabrication thereof are provided. In one aspect, a method of forming a solar cell includes: forming a first transparent contact on a substrate; depositing an n-type layer on the first transparent contact; depositing a p-type chalcogen absorber layer on the n-type layer, wherein a p-n junction is formed between the p-type chalcogen absorber layer and the n-type layer; depositing a protective interlayer onto the p-type chalcogen absorber layer, wherein the protective interlayer fully covers the p-type chalcogen absorber layer; and forming a second transparent contact on the interlayer, wherein the interlayer being disposed between the p-type chalcogen absorber layer and the second transparent contact serves to protect the p-n junction during the forming of the second transparent contact. Solar cells and other methods for formation thereof are also provided.Type: GrantFiled: April 13, 2020Date of Patent: January 17, 2023Assignee: International Business Machines CorporationInventors: Douglas M. Bishop, Yun Seog Lee, Saurabh Singh, Teodor K. Todorov
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Patent number: 11455521Abstract: A neuromorphic semiconductor device includes a copper-based intercalation channel disposed on an insulative layer, a source contact and a drain contact of a substrate. A copper-based electrolyte layer is disposed on the copper-based intercalation channel and a copper-based gate electrode is disposed on the copper-based electrolyte layer.Type: GrantFiled: March 1, 2019Date of Patent: September 27, 2022Assignee: International Business Machines CorporationInventors: Teodor K. Todorov, Douglas M. Bishop, Jianshi Tang, John Rozen
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Patent number: 11411191Abstract: Selenium-fullerene heterojunction solar cells and techniques for fabrication thereof are provided. In one aspect, a method of forming a solar cell includes: forming a front contact on a substrate; depositing an n-type semiconducting layer on the front contact, wherein the n-type semiconducting layer comprises a fullerene or fullerene derivative; forming a p-type chalcogen absorber layer on the n-type semiconducting layer; depositing a high workfunction material onto the p-type chalcogen absorber layer, wherein the high workfunction material has a workfunction of greater than about 5.2 electron volts; and forming a back contact on the high workfunction material. Solar cells and other methods for formation thereof are also provided.Type: GrantFiled: April 13, 2020Date of Patent: August 9, 2022Assignee: International Business Machines CorporationInventors: Douglas M. Bishop, Yun Seog Lee, Saurabh Singh, Teodor K. Todorov
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Publication number: 20220045270Abstract: A method of fabricating a synaptic device is provided. The method includes forming a channel layer between a first terminal and a second terminal. The channel layer varies in resistance based on a magnesium concentration in the channel layer. The method further includes forming an electrolyte layer. The electrolyte layer includes a magnesium ion conductive material. A third terminal is formed over the electrolyte layer and applies a signal to the electrolyte layer and the channel layer.Type: ApplicationFiled: October 7, 2021Publication date: February 10, 2022Inventors: Douglas M. Bishop, Martin Michael Frank, Teodor Krassimirov Todorov
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Patent number: 11201284Abstract: A method of fabricating a synaptic device is provided. The method includes forming a channel layer between a first terminal and a second terminal. The channel layer varies in resistance based on a magnesium concentration in the channel layer. The method further includes forming an electrolyte layer. The electrolyte layer includes a magnesium ion conductive material. A third terminal is formed over the electrolyte layer and applies a signal to the electrolyte layer and the channel layer.Type: GrantFiled: March 24, 2020Date of Patent: December 14, 2021Assignee: International Business Machines CorporationInventors: Douglas M. Bishop, Martin Michael Frank, Teodor Krassimirov Todorov
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Publication number: 20210305504Abstract: A method of fabricating a synaptic device is provided. The method includes forming a channel layer between a first terminal and a second terminal. The channel layer varies in resistance based on a magnesium concentration in the channel layer. The method further includes forming an electrolyte layer. The electrolyte layer includes a magnesium ion conductive material. A third terminal is formed over the electrolyte layer and applies a signal to the electrolyte layer and the channel layer.Type: ApplicationFiled: March 24, 2020Publication date: September 30, 2021Inventors: Douglas M. Bishop, Martin Michael Frank, Teodor Krassimirov Todorov
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Publication number: 20210151669Abstract: Methods of forming variable-resistance devices include forming a variable-resistance layer between a first terminal and a second terminal from a material that varies in resistance based on an oxygen concentration. An electrolyte layer is formed over the variable-resistance layer from a material that is stable at room temperature and that conducts oxygen ions in accordance with an applied voltage. A conductive gate layer is formed over the electrolyte layer.Type: ApplicationFiled: December 23, 2020Publication date: May 20, 2021Inventors: Teodor K. Todorov, Douglas M. Bishop, Jianshi Tang, John Rozen
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Patent number: 11011661Abstract: Improved high work function back contacts for solar cells are provided. In one aspect, a method of forming a solar cell includes: forming a completed solar cell having a substrate coated with an electrically conductive material, an absorber disposed on the electrically conductive material, a buffer layer disposed on the absorber, a transparent front contact disposed on the buffer layer, and a metal grid disposed on the transparent front contact; removing the substrate and the electrically conductive material using exfoliation, exposing a backside surface of the solar cell; depositing a high work function material onto the back side surface of the solar cell; and depositing a back contact onto the high work function material. A solar cell formed by the present techniques is also provided. Yield of the exfoliated device can be improved by removing bubbles from adhesive used for exfoliation and/or forming contact pads to access the metal grid.Type: GrantFiled: January 13, 2020Date of Patent: May 18, 2021Assignee: International Business Machines CorporationInventors: Priscilla D. Antunez, Douglas M. Bishop, Gloria W. Fraczak, Oki Gunawan, Richard A. Haight
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Patent number: 10936944Abstract: A neuromorphic device includes a first electrode layer arranged on a substrate, and an electrolyte layer arranged on the first electrode layer. The electrolyte layer includes a solid electrolyte material. The neuromorphic device further includes an ion permeable, electrically conductive membrane arranged on the electrolyte layer and an ion intercalation layer arranged on the ion permeable, electrically conductive membrane. The neuromorphic device includes a second electrode layer arranged on the ion intercalation layer.Type: GrantFiled: August 22, 2019Date of Patent: March 2, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Teodor K. Todorov, John Rozen, Douglas M. Bishop
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Patent number: 10930844Abstract: Variable-resistance devices and methods of forming the same include a variable-resistance layer, formed between a first terminal and a second terminal, that varies in resistance based on an oxygen concentration in the variable-resistance layer. An electrolyte layer that is stable at room temperature and that conducts oxygen ions in accordance with an applied voltage is positioned over the variable-resistance layer. A gate layer is configured to apply a voltage on the electrolyte layer and the variable-resistance layer and is positioned over the electrolyte layer.Type: GrantFiled: October 11, 2018Date of Patent: February 23, 2021Assignee: International Business Machines CorporationInventors: Teodor K. Todorov, Douglas M. Bishop, Jianshi Tang, John Rozen
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Patent number: 10885431Abstract: A neuromorphic device includes a first electrode layer arranged on a substrate, and an electrolyte layer arranged on the first electrode layer. The electrolyte layer includes a solid electrolyte material. The neuromorphic device further includes an ion permeable, electrically conductive membrane arranged on the electrolyte layer and an ion intercalation layer arranged on the ion permeable, electrically conductive membrane. The neuromorphic device includes a second electrode layer arranged on the ion intercalation layer.Type: GrantFiled: August 22, 2019Date of Patent: January 5, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Teodor K. Todorov, John Rozen, Douglas M. Bishop
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Publication number: 20200387779Abstract: A method of fabricating a neuromorphic device includes forming a variable-resistance layer between a first terminal and a second terminal, the variable-resistance layer varies in resistance based on an oxygen concentration in the variable-resistance layer. The method further includes forming an electrolyte layer over the variable-resistance layer that is stable at room temperature and that conducts oxygen ions in accordance with an applied voltage. The method further includes forming a gate layer over the electrolyte layer to apply a voltage on the electrolyte layer and the variable-resistance layer, the gate layer formed using an oxygen scavenging material.Type: ApplicationFiled: June 10, 2019Publication date: December 10, 2020Inventors: Teodor Krassimirov Todorov, JIANSHI TANG, Douglas M. Bishop, John Rozen, Takashi Ando
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Publication number: 20200287237Abstract: Copper ionic conductor films and method of making the same are provided. In one aspect, a method of forming a crystalline ionic conductor film includes: depositing a mixture of sources for components of the crystalline ionic conductor film onto a substrate, the components including: i) Cu, ii) a component A selected from: Rb, Cs, K, Na and/or Li, and iii) a component B selected from: F, Cl, Br and/or I; and annealing the mixture under conditions sufficient to form the crystalline ionic conductor film on the substrate having a formula: CuxAyBz, wherein 0<x<20, 0<y<10, and 0<z<30. A device having a crystalline ionic conductor film as an electrolyte and method of forming the device are also provided.Type: ApplicationFiled: March 7, 2019Publication date: September 10, 2020Inventors: Teodor K. Todorov, Douglas M. Bishop, John Collins, Frances M. Ross
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Publication number: 20200279154Abstract: A neuromorphic semiconductor device includes a copper-based intercalation channel disposed on an insulative layer, a source contact and a drain contact of a substrate. A copper-based electrolyte layer is disposed on the copper-based intercalation channel and a copper-based gate electrode is disposed on the copper-based electrolyte layer.Type: ApplicationFiled: March 1, 2019Publication date: September 3, 2020Inventors: Teodor K. Todorov, Douglas M. Bishop, Jianshi Tang, John Rozen
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Publication number: 20200243707Abstract: Semitransparent chalcogen solar cells and techniques for fabrication thereof are provided. In one aspect, a method of forming a solar cell includes: forming a first transparent contact on a substrate; depositing an n-type layer on the first transparent contact; depositing a p-type chalcogen absorber layer on the n-type layer, wherein a p-n junction is formed between the p-type chalcogen absorber layer and the n-type layer; depositing a protective interlayer onto the p-type chalcogen absorber layer, wherein the protective interlayer fully covers the p-type chalcogen absorber layer; and forming a second transparent contact on the interlayer, wherein the interlayer being disposed between the p-type chalcogen absorber layer and the second transparent contact serves to protect the p-n junction during the forming of the second transparent contact. Solar cells and other methods for formation thereof are also provided.Type: ApplicationFiled: April 13, 2020Publication date: July 30, 2020Inventors: Douglas M. Bishop, Yun Seog Lee, Saurabh Singh, Teodor K. Todorov
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Publication number: 20200243784Abstract: Selenium-fullerene heterojunction solar cells and techniques for fabrication thereof are provided. In one aspect, a method of forming a solar cell includes: forming a front contact on a substrate; depositing an n-type semiconducting layer on the front contact, wherein the n-type semiconducting layer comprises a fullerene or fullerene derivative; forming a p-type chalcogen absorber layer on the n-type semiconducting layer; depositing a high workfunction material onto the p-type chalcogen absorber layer, wherein the high workfunction material has a workfunction of greater than about 5.2 electron volts; and forming a back contact on the high workfunction material. Solar cells and other methods for formation thereof are also provided.Type: ApplicationFiled: April 13, 2020Publication date: July 30, 2020Inventors: Douglas M. Bishop, Yun Seog Lee, Saurabh Singh, Teodor K. Todorov