Abstract: Systems provide a chassis housing one or more Information Handling Systems (IHSs). A control layer of the chassis includes a power supply for use both in the control layer of the chassis and in a processing layer of the chassis. The control layer also includes a motherboard with CPUs coupled to the processing layer via a PCIe switch fabric. The processing layer includes one or more replaceable I/O modules installed in a front compartment. The processing layer also includes a hardware accelerator sled installed in a central compartment of the processing layer, where the hardware accelerator sled is replaceable via a rear of the processing layer. A block of cooling fans is installed in a rear compartment of the processing layer, where the fans provide airflow cooling to the I/O modules and hardware accelerator sled installed in the processing layer. In this configuration, cooling requirements are met for the chassis.

Abstract: Systems are provided where a chassis houses an Information Handling System (IHS). The chassis includes a motherboard with one or more CPUs configured to operate as a root complex for a PCIe switch fabric that includes a plurality of PCIe devices of the IHS. The chassis also includes an I/O module providing I/O capabilities for the motherboard. The I/O module includes a network controller configured to allocate network bandwidth for use by a hardware accelerator sled installed in the chassis, unless an integrated network controller is detected as a component of a hardware accelerator baseboard installed in the hardware accelerator sled. The I/O module also includes a PCI switch configured to operate with the CPUs as the root complex of the PCIe switch fabric and further configured to operate with the hardware accelerator baseboard as the root complex of the PCIe switch fabric.

Abstract: Systems provide a chassis housing one or more Information Handling Systems (IHSs). A control layer of the chassis includes a power supply for use both in the control layer of the chassis and in a processing layer of the chassis. The control layer also includes a motherboard with CPUs coupled to the processing layer via a PCIe switch fabric. The processing layer includes one or more replaceable I/O modules installed in a front compartment. The processing layer also includes a hardware accelerator sled installed in a central compartment of the processing layer, where the hardware accelerator sled is replaceable via a rear of the processing layer. A block of cooling fans is installed in a rear compartment of the processing layer, where the fans provide airflow cooling to the I/O modules and hardware accelerator sled installed in the processing layer. In this configuration, cooling requirements are met for the chassis.

Abstract: Systems are provided where a chassis houses an Information Handling System (IHS). The chassis includes a motherboard with one or more CPUs configured to operate as a root complex for a PCIe switch fabric that includes a plurality of PCIe devices of the IHS. The chassis also includes an I/O module providing I/O capabilities for the motherboard. The I/O module includes a network controller configured to allocate network bandwidth for use by a hardware accelerator sled installed in the chassis, unless an integrated network controller is detected as a component of a hardware accelerator baseboard installed in the hardware accelerator sled. The I/O module also includes a PCI switch configured to operate with the CPUs as the root complex of the PCIe switch fabric and further configured to operate with the hardware accelerator baseboard as the root complex of the PCIe switch fabric.

Abstract: A computing apparatus including a printed circuit board (PCB) including a first central processing unit (CPU) socket and additional CPU socket(s); a CPU coupled to the first CPU socket; a base interposer coupled to the additional CPU socket(s); and one or more devices connected to the base interposer, wherein the base interposer provides a connection between the CPU and the one or more devices.

Abstract: A computing apparatus including a printed circuit board (PCB) including a first central processing unit (CPU) socket and additional CPU socket(s); a CPU coupled to the first CPU socket; a base interposer coupled to the additional CPU socket(s); and one or more devices connected to the base interposer, wherein the base interposer provides a connection between the CPU and the one or more devices.