Patents by Inventor Douglas W. Kemerer
Douglas W. Kemerer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8756554Abstract: A method comprises tracing a first and second terminal of a junction through a circuit layout to associated power supplies to determine their respective defined bias values. The method further comprises comparing the defined bias values of each terminal in order to determine, based on the comparison, whether the junction is forward biased.Type: GrantFiled: May 15, 2012Date of Patent: June 17, 2014Assignee: International Business Machines CorporationInventors: Douglas W. Kemerer, Edward W. Seibert, Lijiang L. Wang
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Publication number: 20130067425Abstract: A method comprises tracing a first and second terminal of a junction through a circuit layout to associated power supplies to determine their respective defined bias values. The method further comprises comparing the defined bias values of each terminal in order to determine, based on the comparison, whether the junction is forward biased.Type: ApplicationFiled: May 15, 2012Publication date: March 14, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Douglas W. Kemerer, Edward W. Seibert, Lijiang L. Wang
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Patent number: 8191030Abstract: A method comprises tracing a first and second terminal of a junction through a circuit layout to associated power supplies to determine their respective defined bias values. The method further comprises comparing the defined bias values of each terminal in order to determine, based on the comparison, whether the junction is forward biased.Type: GrantFiled: December 17, 2008Date of Patent: May 29, 2012Assignee: International Business Machines CorporationInventors: Douglas W. Kemerer, Edward W. Seibert, Lijiang L. Wang
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Patent number: 7941780Abstract: A design rule that determines a degree of overlap between two design elements in two adjoining levels by estimating a physical overlap area, or an “intersect area,” of corresponding structures in a semiconductor chip is provided. The estimation of the physical intersect area may factor in line edge biasing, critical dimension tolerance, overlay tolerance, and corner rounding to provide an accurate estimate of a physical area for each of the structures corresponding to the two design elements. The intersect area is employed as a metric to determine compliance with a ground rule, i.e., the ground rule is specified in terms of the intersect region. Other derived quantities such as electrical resistance, electromigration resistance, expected yield may be calculated from the intersect area, and may be advantageously employed to optimize the design data.Type: GrantFiled: April 18, 2008Date of Patent: May 10, 2011Assignee: International Business Machines CorporationInventors: Albrik Avanessian, Henry A. Bonges, III, Dureseti Chidambarrao, Stephen E. Greco, Douglas W. Kemerer, Tina Wagner
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Patent number: 7849426Abstract: The embodiments of the invention provide a design structure for detection and compensation of negative bias temperature instability (NBTI) induced threshold degradation. A semiconductor device is provided comprising at least one stress device having a voltage applied to its gate node and at least one reference device having a zero gate-to-source voltage. A controller is also provided to configure node voltages of the device and/or the reference device to reflect different regions of device operations found in digital and analog circuit applications. Moreover, the controller measures a difference in current between the stress device and the reference device to determine whether NBTI induced threshold degradation has occurred in the stress device. The controller also adjusts an output power supply voltage of the stress device until a performance of the stress device matches a performance of the reference device to account for the NBTI induced threshold degradation.Type: GrantFiled: October 31, 2007Date of Patent: December 7, 2010Assignee: International Business Machines CorporationInventors: Kenneth J. Goodnow, Douglas W. Kemerer, Stephen G. Shuma, Oscar C. Strohacker, Mark S. Styduhar, Peter A. Twombly, Paul S. Zuchowski
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Patent number: 7696811Abstract: A design structure. The design structure includes: a first set of FETs having a designed first Vt and a second set of FETs having a designed second Vt, the first Vt different from the second Vt; a first monitor circuit containing at least one FET of the first set of FETs and a second monitor circuit containing at least one FET of the second set of FETs; a compare circuit configured to generate a compare signal based on a performance measurement of the first monitor circuit and of the second monitor circuit; a control unit responsive to the compare signal and configured to generate a control signal regulator based on the compare signal; and an adjustable voltage regulator responsive to the control signal and configured to voltage bias wells of FETs of the second set of FETs, the value of the voltage bias applied based on the control signal.Type: GrantFiled: November 16, 2007Date of Patent: April 13, 2010Assignee: International Business Machines CorporationInventors: Corey Kenneth Barrows, Douglas W. Kemerer, Stephen Gerard Shuma, Douglas Willard Stout, Oscar Conrad Strohacker, Mark Steven Styduhar, Paul Steven Zuchowski
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Patent number: 7671666Abstract: A circuit and a method for adjusting the performance of an integrated circuit, the method includes: comprising: (a) measuring the performance of a first monitor circuit having at least one field effect transistor (FET) of a first set of FETs, each FET of the first set of FETs having a designed first threshold voltage; (b) measuring the performance of a second monitor circuit having at least one field effect transistor (FET) of a second set of FETs, each FET of the second set of FETs having a designed second threshold voltage, the second threshold voltage different from the first threshold voltage; and (c) applying a bias voltage to wells of the FETs of the second set of FETs based on comparing a measured performance of the first and second monitor circuits to specified performances of the first and second monitor circuits.Type: GrantFiled: July 9, 2008Date of Patent: March 2, 2010Assignee: International Business Machines CorporationInventors: Corey Kenneth Barrows, Douglas W. Kemerer, Stephen Gerard Shuma, Douglas Willard Stout, Oscar Conrad Strohacker, Mark Steven Styduhar, Paul Steven Zuchowski
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Patent number: 7619398Abstract: Disclosed herein is a system for controlling power supply voltage to an on-chip power distribution network. The system incorporates a programmable on-chip sensing network that can be selectively connected to the power distribution network at multiple locations. When the sensing network is selectively connected to the power distribution network at an optimal sensing point, a local voltage feedback signal from that optimal sensing point is generated and used to adjust the power supply voltage and, thus, to manage voltage distribution across the power distribution network. Additionally, the system incorporates a policy for managing the voltage distribution across the power distribution network, a means for profiling voltage drops across the power distribution network and a means for selecting the optimal sensing point based on the policy and the profile. Another embodiment of the system can further control power supply voltages to multiple power distribution networks on the same chip.Type: GrantFiled: May 14, 2008Date of Patent: November 17, 2009Assignee: International Business Machines CorporationInventors: Corey K. Barrows, Douglas W. Kemerer, Douglas W. Stout, Peter A. Twombly
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Publication number: 20090265673Abstract: A design rule that determines a degree of overlap between two design elements in two adjoining levels by estimating a physical overlap area, or an “intersect area,” of corresponding structures in a semiconductor chip is provided. The estimation of the physical intersect area may factor in line edge biasing, critical dimension tolerance, overlay tolerance, and corner rounding to provide an accurate estimate of a physical area for each of the structures corresponding to the two design elements. The intersect area is employed as a metric to determine compliance with a ground rule, i.e., the ground rule is specified in terms of the intersect region. Other derived quantities such as electrical resistance, electromigration resistance, expected yield may be calculated from the intersect area, and may be advantageously employed to optimize the design data.Type: ApplicationFiled: April 18, 2008Publication date: October 22, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Albrik Avanessian, Henry A. Bonges, III, Dureseti Chidambarrao, Stephen E. Greco, Douglas W. Kemerer, Tina Wagner
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Publication number: 20090150842Abstract: A method comprises tracing a first and second terminal of a junction through a circuit layout to associated power supplies to determine their respective defined bias values. The method further comprises comparing the defined bias values of each terminal in order to determine, based on the comparison, whether the junction is forward biased.Type: ApplicationFiled: December 17, 2008Publication date: June 11, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Douglas W. Kemerer, Edward W. Seibert, Lijiang L. Wang
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Publication number: 20090113358Abstract: The embodiments of the invention provide a design structure for detection and compensation of negative bias temperature instability (NBTI) induced threshold degradation. A semiconductor device is provided comprising at least one stress device having a voltage applied to its gate node and at least one reference device having a zero gate-to-source voltage. A controller is also provided to configure node voltages of the device and/or the reference device to reflect different regions of device operations found in digital and analog circuit applications. Moreover, the controller measures a difference in current between the stress device and the reference device to determine whether NBTI induced threshold degradation has occurred in the stress device. The controller also adjusts an output power supply voltage of the stress device until a performance of the stress device matches a performance of the reference device to account for the NBTI induced threshold degradation.Type: ApplicationFiled: October 31, 2007Publication date: April 30, 2009Inventors: Kenneth J. Goodnow, Douglas W. Kemerer, Stephen G. Shuma, Oscar C. Strohacker, Mark S. Styduhar, Peter A. Twombly, Paul S. Zuchowski
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Patent number: 7504847Abstract: The embodiments of the invention provide an apparatus and method for detection and compensation of negative bias temperature instability (NBTI) induced threshold degradation. A semiconductor device is provided comprising at least one stress device having a voltage applied to its gate node and at least one reference device having a zero gate-to-source voltage. A controller is also provided to configure node voltages of the device and/or the reference device to reflect different regions of device operations found in digital and analog circuit applications. Moreover, the controller measures a difference in current between the stress device and the reference device to determine whether NBTI induced threshold degradation has occurred in the stress device. The controller also adjusts an output power supply voltage of the stress device until a performance of the stress device matches a performance of the reference device to account for the NBTI induced threshold degradation.Type: GrantFiled: October 19, 2006Date of Patent: March 17, 2009Assignee: International Business Machines CorporationInventors: Kenneth J. Goodnow, Douglas W. Kemerer, Stephen G. Shuma, Oscar C. Strohacker, Mark S. Styduhar, Peter A. Twembly, Paul S. Zuchewski
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Patent number: 7490303Abstract: A method comprises tracing a first and second terminal of a junction through a circuit layout to associated power supplies to determine their respective defined bias values. The method further comprises comparing the defined bias values of each terminal in order to determine, based on the comparison, whether the junction is forward biased.Type: GrantFiled: March 3, 2006Date of Patent: February 10, 2009Assignee: International Business Machines CorporationInventors: Douglas W. Kemerer, Edward W. Seibert, Lijiang L. Wang
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Patent number: 7459958Abstract: A circuit and a method for adjusting the performance of an integrated circuit, the circuit includes: first and second sets of FETs having respective first and second threshold voltages, the first threshold voltage different from the second threshold voltage; a first monitor circuit containing at least one FET of the first set of FETs and a second monitor circuit containing at least one FET of the second set of FETs; a compare circuit adapted to generate a compare signal based on a performance measurement of the first monitor circuit and a performance measurement of the second monitor circuit; and a control unit adapted to generate a control signal to a voltage regulator based on the compare signal, the voltage regulator adapted to supply a bias voltage to wells of FETs of the second set of FETs, the value of the bias voltage based on the control signal.Type: GrantFiled: June 19, 2006Date of Patent: December 2, 2008Assignee: International Business Machines CorporationInventors: Corey Kenneth Barrows, Douglas W. Kemerer, Stephen Gerard Shuma, Douglas Willard Stout, Oscar Conrad Strohacker, Mark Steven Styduhar, Paul Steven Zuchowski
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Publication number: 20080265983Abstract: A circuit and a method for adjusting the performance of an integrated circuit, the method includes: comprising: (a) measuring the performance of a first monitor circuit having at least one field effect transistor (FET) of a first set of FETs, each FET of the first set of FETs having a designed first threshold voltage; (b) measuring the performance of a second monitor circuit having at least one field effect transistor (FET) of a second set of FETs, each FET of the second set of FETs having a designed second threshold voltage, the second threshold voltage different from the first threshold voltage; and (c) applying a bias voltage to wells of the FETs of the second set of FETs based on comparing a measured performance of the first and second monitor circuits to specified performances of the first and second monitor circuits.Type: ApplicationFiled: July 9, 2008Publication date: October 30, 2008Inventors: Corey Kenneth Barrows, Douglas W. Kemerer, Stephen Gerard Shuma, Douglas Willard Stout, Oscar Conrad Strohacker, Mark Steven Styduhar, Paul Steven Zuchowski
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Publication number: 20080246533Abstract: A circuit and a method for adjusting the performance of an integrated circuit, the circuit includes: first and second sets of FETs having respective first and second threshold voltages, the first threshold voltage different from the second threshold voltage; a first monitor circuit containing at least one FET of the first set of FETs and a second monitor circuit containing at least one FET of the second set of FETs; a compare circuit configured to generate a compare signal based on a performance measurement of the first monitor circuit and a performance measurement of the second monitor circuit; and a control unit configured to generate a control signal to a voltage regulator based on the compare signal, the voltage regulator configured to supply a bias voltage to wells of FETs of the second set of FETs, the value of the bias voltage based on the control signal.Type: ApplicationFiled: June 13, 2008Publication date: October 9, 2008Inventors: Corey Kenneth Barrows, Douglas W. Kemerer, Stephen Gerard Shuma, Douglas Willard Stout, Oscar Conrad Strohacker, Mark Steven Styduhar, Paul Steven Zuchowski
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Publication number: 20080211472Abstract: Disclosed herein is a system for controlling power supply voltage to an on-chip power distribution network. The system incorporates a programmable on-chip sensing network that can be selectively connected to the power distribution network at multiple locations. When the sensing network is selectively connected to the power distribution network at an optimal sensing point, a local voltage feedback signal from that optimal sensing point is generated and used to adjust the power supply voltage and, thus, to manage voltage distribution across the power distribution network. Additionally, the system incorporates a policy for managing the voltage distribution across the power distribution network, a means for profiling voltage drops across the power distribution network and a means for selecting the optimal sensing point based on the policy and the profile. Another embodiment of the system can further control power supply voltages to multiple power distribution networks on the same chip.Type: ApplicationFiled: May 14, 2008Publication date: September 4, 2008Applicant: International Business Machines CorporationInventors: Corey K. Barrows, Douglas W. Kemerer, Douglas W. Sinut, Peter A. Twombly
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Patent number: 7397228Abstract: Disclosed herein is a system for controlling power supply voltage to an on-chip power distribution network. The system incorporates a programmable on-chip sensing network that can be selectively connected to the power distribution network at multiple locations. When the sensing network is selectively connected to the power distribution network at an optimal sensing point, a local voltage feedback signal from that optimal sensing point is generated and used to adjust the power supply voltage and, thus, to manage voltage distribution across the power distribution network. Additionally, the system incorporates a policy for managing the voltage distribution across the power distribution network, a means for profiling voltage drops across the power distribution network and a means for selecting the optimal sensing point based on the policy and the profile. Another embodiment of the system can further control power supply voltages to multiple power distribution networks on the same chip.Type: GrantFiled: January 12, 2006Date of Patent: July 8, 2008Assignee: International Business Machines CorporationInventors: Corey K. Barrows, Douglas W. Kemerer, Douglas W. Sinut, Peter A. Twombly
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Publication number: 20080122524Abstract: A circuit and a method for adjusting the performance of an integrated circuit, the circuit includes: first and second sets of FETs having respective first and second threshold voltages, the first threshold voltage different from the second threshold voltage; a first monitor circuit containing at least one FET of the first set of FETs and a second monitor circuit containing at least one FET of the second set of FETs; a compare circuit adapted to generate a compare signal based on a performance measurement of the first monitor circuit and a performance measurement of the second monitor circuit; and a control unit adapted to generate a control signal to a voltage regulator based on the compare signal, the voltage regulator adapted to supply a bias voltage to wells of FETs of the second set of FETs, the value of the bias voltage based on the control signal.Type: ApplicationFiled: June 19, 2006Publication date: May 29, 2008Inventors: Corey Kenneth Barrows, Douglas W. Kemerer, Stephen Gerard Shuma, Douglas Willard Stout, Oscar Conrad Strohacker, Mark Steven Styduhar, Paul Steven Zuchowski
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Publication number: 20080094092Abstract: The embodiments of the invention provide an apparatus and method for detection and compensation of negative bias temperature instability (NBTI) induced threshold degradation. A semiconductor device is provided comprising at least one stress device having a voltage applied to its gate node and at least one reference device having a zero gate-to-source voltage. A controller is also provided to configure node voltages of the device and/or the reference device to reflect different regions of device operations found in digital and analog circuit applications. Moreover, the controller measures a difference in current between the stress device and the reference device to determine whether NBTI induced threshold degradation has occurred in the stress device. The controller also adjusts an output power supply voltage of the stress device until a performance of the stress device matches a performance of the reference device to account for the NBTI induced threshold degradation.Type: ApplicationFiled: October 19, 2006Publication date: April 24, 2008Inventors: Kenneth J Goodnow, Douglas W. Kemerer, Stephen G. Shuma, Oscar C. Strohacker, Mark S. Styduhar, Peter A. Twembly, Paul S. Zuchewski