Abstract: Various enhancements are made to the architecture of a list processor to facilitate its use in implementing a message queue that is shared by queue managers residing across a multisystem complex. A new list structure control—a program list entry identifier indicator, or PLEIDI—is defined to allow the user to specify whether user-defined entry IDs are used when the list is allocated. A new delete list (DL) command is added that sequentially processes list entries in the order in which they exist on the specified list. A new move list entries (MLES) command provides a performance-optimized means to process an input list of entries. New key comparison functions and list monitoring enhancements have also been added. A new type of key called a secondary list entry key (SLEK) allows the user to specify a secondary key value as a means to identify a list entry.

Abstract: A method and apparatus for implementing a shared message queue using a list structure. A put list is defined comprising a sequence of list entries, each of which corresponds to a message in the queue and has an associated list entry key. Each list entry key corresponding to an uncommitted message falls within an uncommitted key range defining an uncommitted portion of the put list, while each list entry key corresponding to a committed message falls within a committed key range defining a committed portion of the put list. To write a message to the queue, a list entry is added to the put list having a list entry key within the uncommitted key range.

Abstract: A coupling facility is coupled to one or more other coupling facilities via one or more peer links. The coupling of the facilities enables various functions to be supported, including the duplexing of structures of the coupling facilities. Duplexing is performed on a structure basis, and thus, a coupling facility may include duplexed structures, as well as non-duplexed or simplexed structures.

Abstract: A lock structure, which includes many entries, is partitioned into segments. A number of the segments are cleaned up in parallel, such that cleanup processing of the entire lock structure is optimized. The lock structure is maintained within a coupling facility, which provides access to the lock structure by one or more processors coupled to the coupling facility. The cleaning up of the lock structure is performed by commands driven by the one or more processors and executed within the coupling facility.

Abstract: A lock structure, which includes many entries, is partitioned into segments. A number of the segments are cleaned up in parallel, such that cleanup processing of the entire lock structure is optimized. The lock structure is maintained within a coupling facility, which provides access to the lock structure by one or more processors coupled to the coupling facility. The cleaning up of the lock structure is performed by commands driven by the one or more processors and executed within the coupling facility.

Abstract: A lock structure, which includes many entries, is partitioned into segments. A number of the segments are cleaned up in parallel, such that cleanup processing of the entire lock structure is optimized. The lock structure is maintained within a coupling facility, which provides access to the lock structure by one or more processors coupled to the coupling facility. The cleaning up of the lock structure is performed by commands driven by the one or more processors and executed within the coupling facility.

Abstract: A system for the transmission of information between elements of a data processing complex and a method for establishing such a system. Two elements of a data processing system are connected by a physical link comprising multiple conductors attached to transceivers at channels in each data processing element. Once the transceivers have been synchronized, commands and responses are exchanged which ensure that all of the transceivers in a channel are connected to the same channel on the other end of the conductor. If the transceivers are considered configured and an entry is made in a Configured-Transceiver table. A search is made of an Allowed-Operational-Link table which contains sets of transceivers which are allowed to become operational links. The set of transceivers thus found, is compared against the Configured-Transceiver-Table to verify that all of the members of the set have been configured. If a match is fondled, this set of transceivers becomes an Intended-Operational-Link.

Abstract: A system for the transmission of information between elements of a data processing complex and a method for establishing such a system. Two elements of a data processing system are connected by a physical link comprising multiple conductors attached to transceivers at channels in each data processing element. Once the transceivers have been synchronized, commands and responses are exchanged which ensure that all of the transceivers in a channel are connected to the same channel on the other end of the conductor. If the transceivers are considered configured an entry is made in a Configured-Transceiver table. A search is made of an Allowed-Operational-Link table which contains sets of transceivers which are allowed to become operational links. The set of transceivers thus found, is compared against the Configured-Transceiver-Table to verify that all of the members of the set have been configured. If a match is found, this set of transceivers becomes an Intended-Operational-Link.

Abstract: A system for the transmission of information between elements of a data processing complex and a method for establishing such a system. Two elements of a data processing system are connected by a physical link comprising multiple conductors attached to transceivers at channels in each data processing element. Once the transceivers have been synchronized, commands and responses are exchanged which ensure that all of the transceivers in a channel are connected to the same channel on the other end of the conductor. If the transceivers are considered configured an entry is made in a Configured-Transceiver table. A search is made of an Allowed-Operational-Link table which contains sets of transceivers which are allowed to become operational links. The set of transceivers thus found, is compared against the Configured-Transceiver-Table to verify that all of the members of the set have been configured. If a match is found, this set of transceivers becomes an Intended-Operational-Link.

Abstract: A system for the transmission of information between elements of a data processing complex and a method for establishing such a system. Two elements of a data processing system are connected by a physical link comprising multiple conductors attached to transceivers at channels in each data processing element. Once the transceivers have been synchronized, commands and responses are exchanged which ensure that all of the transceivers in a channel are connected to the same channel on the other end of the conductor. If the transceivers are considered configured and an entry is made in a Configured-Transceiver table. A search is made of an Allowed-Operational-Link table which contains sets of transceivers which are allowed to become operational links. The set of transceivers thus found, is compared against the Configured-Transceiver-Table to verify that all of the members of the set have been configured. If a match is found, this set of transceivers becomes an Intended-Operational-Link.

Abstract: A system and method for asynchronously transmitting data blocks, in parallel, across multiple fibers in a serial manner. Frame groups are provided as a mechanism to transmit associated data serially on each fiber and tie the data being transmitted together. The frame groups do not have sequence numbers, therefore, the receiver determines which frames are part of a frame group by the arrival times of the individual frames. In one embodiment, the transceivers for each member of the parallel bus asynchronously achieve synchronism at each end of the fiber. Thus the need for a common clock is eliminated. The receivers on each side of the bus determine the relative skew for each conductor by performing skew measurements on a calibration message generated by the transmitters on the other side of the bus. When the skew on all conductors, viewed from both sides of the bus, has been determined, the skew values are exchanged across the bus, thus enabling the transmitters to set proper frame spacing.

Abstract: A system for the transmission of information between elements of a data processing complex and a method for establishing such a system. Two elements of a data processing system are connected by a physical link comprising multiple conductors attached to transceivers at channels in each data processing element. Once the transceivers have been synchronized, commands and responses are exchanged which ensure that all of the transceivers in a channel are connected to the same channel on the other end of the conductor. If the transceivers are considered configured an entry is made in a Configured-Transceiver table. A search is made of an Allowed-Operational-Link table which contains sets of transceivers which are allowed to become operational links. The set of transceivers thus found, is compared against the Configured-Transceiver-Table to verify that all of the members of the set have been configured. If a match is found, this set of transceivers becomes an Intended-Operational-Link.

Abstract: Buffers are provided in two elements between which data is to be transferred wherein both buffers are managed solely by the originator of the data transfer. Only one transfer is required to transmit a message, and a second transfer acknowledges the completion of the function because message delivery to the receiver is guaranteed under the implemented protocol. When a request is sent, a message timer is started at the sender. When the normal response for the request is received, the timer is reset; however, if the duration of the message operation exceeds the timeout value, a message-timeout procedure is initiated. When the cancel command is issued, a second timer is set. If this timer is exceeded, subsequent cancel commands can be issued. If subsequent cancel commands are issued, a cancel complete command must be sent and responded to.

Abstract: A system for the transmission of information between elements of a data processing complex and a method for establishing such a system. Two elements of a data processing system are connected by a physical link comprising multiple conductors attached to transceivers at channels in each data processing element. Once the transceivers have been synchronized, commands and responses are exchanged which ensure that all of the transceivers in a channel are connected to the same channel on the other end of the conductor. If the transceivers are considered configured and an entry is made in a Configured-Transceiver table. A search is made of an Allowed-Operational-Link table which contains sets of transceivers which are allowed to become operational links. The set of transceivers thus found, is compared against the Configured-Transceiver-Table to verify that all of the members of the set have been configured. If a match is found, this set of transceivers becomes an Intended-Operational-Link.

Abstract: A system and method for asynchronously transmitting data blocks, in parallel, across multiple fibers in a serial manner. Frame groups are provided as a mechanism to transmit associated data serially on each fiber and tie the data being transmitted together. The frame groups do not have sequence numbers, therefore, the receiver determines which frames are part of a frame group by the arrival times of the individual frames. In one embodiment, the transceivers for each member of the parallel bus asynchronously achieve synchronism at each end of the fiber. Thus the need for a common clock is eliminated. The receivers on each side of the bus determine the relative skew for each conductor by performing skew measurements on a calibration message generated by the transmitters on the other side of the bus. When the skew on all conductors, viewed from both sides of the bus, has been determined, the skew values are exchanged across the bus, thus enabling the transmitters to set proper frame spacing.

Abstract: A system and method for instrumenting the execution of instructions in an out-of-sequence execution machine. Instructions tagged with a preselected instruction identification number (IID) are identified. When an instruction having the preselected IID is encountered, information associated with that instruction is saved as the out-of-sequence execution proceeds. If the instruction completes, the information is stored as a single instrumentation entry in a memory array. If the instruction does not complete, the information is disposed of. The process id repeated for each instruction having the preselected IID until the memory array is full. The storage of instruction information in the memory can be further conditioned on the occurrence of a cache miss or other system conditions.

Abstract: An edge triggered polarity hold, clocked latch circuit is disclosed which requires the use of only a single clock line for operation. The latch circuit comprises three set-reset type latches. Each of two latches receives one set and one reset signal. The third latch receives two reset signals and one set signal. A single clock signal is applied jointly to a reset terminal of the third latch and of one of the first two latches. A data signal is applied to the set terminal of the third latch. The other of the first two latches constitutes the output latch and is connected to receive the outputs of the remaining latches. The output latch produces an output equal to an input data signal upon each occurrence of the leading edge of an input clock signal. The output is held (latched) until the occurrence of the next clock signal when the output becomes equal to the then existing input data signal.

Abstract: A latching circuit with reduced signal delay is disclosed comprising a latch and an output logic function circuit. The same signals are applied to the output gate of the latch and to the logic function circuit, whereby the output gate and the logic function circuit effectively are connected in parallel, rather than in series, to eliminate one level of logic delay. An additional logic signal is applied only to the logic function circuit but not to the latch. Provision can be made for applying inverted data to the latch in the event that the latch and the logic function circuit are implemented with NAND or NOR gates.

Abstract: A hazard-free latch is disclosed comprising three NAND logic gates, one of the gates, in combination with its output loading, being relatively fast and another of the gates, in combination with its output loading, being relatively slow. Both gates receive an input clock signal. Input data is applied to the third gate. The output of the fast gate is connected to another input of the slow gate. The outputs of the third and the slow gates are connected to an output terminal and to another input of the fast gate.

Abstract: An integrated circuit chip having an embedded array which is not directly accessible from the primary input/output chip pins is manufactured with additional test circuitry directly on the chip, such that the performance of the array may be physically tested from the input/output pins by an external chip tester while the array remains embedded. Because of the added test circuitry, tests are not limited to the original chip architecture, and a variety of array tests may be made by an external tester without redesigning the chip architecture.