Patents by Inventor Duk Hong

Duk Hong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11756300
    Abstract: Disclosed are a method and apparatus for summarization of unsupervised video with efficient key frame selection reward functions. Frame-level visual features are extracted from an input video. An attention weight is computed and an importance score is represented as a frame tracking probability for selecting a key frame using the attention weight. A temporal consistency reward function and a representativeness reward function are obtained so as to select the key frame, based on a visual similarity distance and temporal distance between key frames, and an attention-based video summarization network is trained to predict an importance score for selecting a key frame of a video summary by using the temporal consistency reward function and the representativeness reward function.
    Type: Grant
    Filed: April 27, 2022
    Date of Patent: September 12, 2023
    Assignee: INHA UNIVERISTY RESEARCH AND BUSINESS FOUNDATION
    Inventors: Geun Sik Jo, Ui Nyoung Yoon, Myung Duk Hong
  • Publication number: 20230281991
    Abstract: Disclosed are a method and apparatus for summarization of unsupervised video with efficient key frame selection reward functions. Frame-level visual features are extracted from an input video. An attention weight is computed and an importance score is represented as a frame tracking probability for selecting a key frame using the attention weight. A temporal consistency reward function and a representativeness reward function are obtained so as to select the key frame, based on a visual similarity distance and temporal distance between key frames, and an attention-based video summarization network is trained to predict an importance score for selecting a key frame of a video summary by using the temporal consistency reward function and the representativeness reward function.
    Type: Application
    Filed: April 27, 2022
    Publication date: September 7, 2023
    Inventors: Geun Sik Jo, Ui Nyoung Yoon, Myung Duk Hong
  • Publication number: 20230079250
    Abstract: A method for generating a model using a virtual target, and a system configured to generate a model using a virtual target are provided. The method for generating a model using a virtual target includes performing machine learning based on previous generation data stored in a database to generate the virtual target of a current generation, and extracting parameters related to the virtual target, and determining values of the extracted parameters based on the virtual target to generate a model.
    Type: Application
    Filed: July 11, 2022
    Publication date: March 16, 2023
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Ji Hye SHIN, Min Kyoung KIM, Jeong Min LEE, Sang Hoon MYUNG, Hyo Won MOON, Sung Jin KIM, Sung Duk HONG
  • Publication number: 20230031793
    Abstract: A simulation system is provided. The simulation system comprises a processor, and a storage to store a simulation program that, when executed by the processor, causes the processor to, use a finite difference method (FDM) to calculate heat energy data generated by light energy provided to a simulation domain, receive the calculated heat energy data and use a finite-element method (FEM) to calculate temperature change data of the simulation domain over time and calculate phase change data of the simulation domain over time, and calculate a silicon loss of the simulation domain using the calculated temperature change data and the calculated phase change.
    Type: Application
    Filed: April 19, 2022
    Publication date: February 2, 2023
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Seung Hyun KIM, Joo Hyun JEON, Jae Seong PARK, Sung Jin KIM, Sung Duk HONG
  • Patent number: 8981480
    Abstract: A semiconductor device includes a buried well, first and second active regions, an isolation layer, and a low resistance region. The buried well is disposed on a substrate and has impurity ions of a first conductivity type. The first and second active regions are disposed on the buried well and each have impurity ions of a second conductivity type, which is different from the first conductivity type. The isolation layer is disposed between the first and second active regions. The low resistance region is disposed between the isolation layer and the substrate and has impurity ions of the second conductivity type. The concentration of impurity ions in the low resistance region is greater than the concentration of the impurity ions in each of the first and second active regions.
    Type: Grant
    Filed: July 12, 2011
    Date of Patent: March 17, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jun-Hee Lim, Satoru Yamada, Sung-Duk Hong
  • Publication number: 20120049256
    Abstract: A semiconductor device includes a buried well, first and second active regions, an isolation layer, and a low resistance region. The buried well is disposed on a substrate and has impurity ions of a first conductivity type. The first and second active regions are disposed on the buried well and each have impurity ions of a second conductivity type, which is different from the first conductivity type. The isolation layer is disposed between the first and second active regions. The low resistance region is disposed between the isolation layer and the substrate and has impurity ions of the second conductivity type. The concentration of impurity ions in the low resistance region is greater than the concentration of the impurity ions in each of the first and second active regions.
    Type: Application
    Filed: July 12, 2011
    Publication date: March 1, 2012
    Inventors: Jun-Hee Lim, Satoru Yamada, Sung-Duk Hong
  • Publication number: 20070072406
    Abstract: Methods of forming metal interconnect structures include forming a first electrically insulating layer on a semiconductor substrate and forming a second electrically insulating layer on the first electrically insulating layer. The second and first electrically insulating layers are selectively etched in sequence to define a contact hole therein. A first metal layer (e.g., tungsten) is deposited. This first metal layer extends on the second electrically insulating layer and into the contact hole. The first metal layer is then patterned to expose the second electrically insulating layer. The second electrically insulating layer is selectively etched for a sufficient duration to expose the first electrically insulating layer and expose a metal plug within the contact hole. This selective etching step is performed using the patterned first metal layer as an etching mask. A seam within the exposed metal plug is then filled with an electrically conductive filler material (e.g., CoWP).
    Type: Application
    Filed: September 28, 2005
    Publication date: March 29, 2007
    Inventors: Kyoung Lee, Ja-Hum Ku, Duk Hong, Wan Park
  • Publication number: 20070045123
    Abstract: Methods of forming metal interconnect layers include forming an electrically insulating layer having a contact hole therein, on a semiconductor substrate and then forming a recess in the electrically insulating layer, at a location adjacent the contact hole. The contact hole and the recess are then filled with a first electrically conductive material (e.g., tungsten (W)). At least a portion of the first electrically conductive material within the contact hole is then exposed. This exposure occurs by etching back a portion of the electrically insulating layer using the first electrically conductive material within the contact hole and within the recess as an etching mask. The first electrically conductive material within the recess is then removed to expose another portion of the electrically insulating layer. Following this, the exposed portion of the first electrically conductive material is covered with a second electrically conductive material (e.g.
    Type: Application
    Filed: August 31, 2005
    Publication date: March 1, 2007
    Inventors: Duk Hong, Kyoung Lee, Markus Naujok, Roman Knoefler
  • Publication number: 20060213126
    Abstract: The present invention relates to an improved method for preparing a polishing slurry, comprising dispersing polishing particles and an anionic polymeric acid in water and then adding to the resulting dispersion an alkaline material in an amount of 0.1 to 8 weight parts based on 100 weight parts of the polishing particles. The polishing slurry obtained by the inventive method exhibits good dispersion stability and non-Prestonian polishing performance, which can be beneficially employed in chemical mechanical polishing of various precision electronic devices.
    Type: Application
    Filed: March 24, 2006
    Publication date: September 28, 2006
    Inventors: Yun Cho, In Lee, Hoon Jeon, Duk Hong, Taiyoung Kim, Sangick Lee, Eunkyoung Park