Patents by Inventor Durai Vishak Nirmal Ramaswamy

Durai Vishak Nirmal Ramaswamy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180331283
    Abstract: An array of cross point memory cells comprises spaced first lines which cross spaced second lines. Two memory cells are individually between one of two immediately adjacent of the second lines and a same single one of the first lines.
    Type: Application
    Filed: July 20, 2018
    Publication date: November 15, 2018
    Applicant: Micron Technology, Inc.
    Inventors: Scott E. Sills, Durai Vishak Nirmal Ramaswamy, Alessandro Calderoni
  • Publication number: 20180315658
    Abstract: A method of forming an array comprising pairs of vertically opposed capacitors comprises forming a conductive lining in individual capacitor openings in insulative-comprising material. An elevational mid-portion of individual of the conductive linings is removed to form an upper capacitor electrode lining and a lower capacitor electrode lining that are elevationally separate and spaced from one another in the individual capacitor openings. A capacitor insulator is formed laterally inward of the upper and lower capacitor electrode linings in the individual capacitor openings. Conductive material is formed laterally inward of the capacitor insulator in the individual capacitor openings and elevationally between the capacitor electrode linings. The conductive material is formed to comprise a shared capacitor electrode that is shared by vertically opposed capacitors in individual of the pairs of vertically opposed capacitors. Additional methods and structure independent of method are disclosed.
    Type: Application
    Filed: June 14, 2018
    Publication date: November 1, 2018
    Applicant: Micron Technology, Inc.
    Inventor: Durai Vishak Nirmal Ramaswamy
  • Publication number: 20180315859
    Abstract: Some embodiments include transistor constructions having a first insulative structure lining a recess within a base. A first conductive structure lines an interior of the first insulative structure, and a ferroelectric structure lines an interior of the first conductive structure. A second conductive structure is within a lower region of the ferroelectric structure, and the second conductive structure has an uppermost surface beneath an uppermost surface of the first conductive structure. A second insulative structure is over the second conductive structure and within the ferroelectric structure. A pair of source/drain regions are adjacent an upper region of the first insulative structure and are on opposing sides of the first insulative structure from one another.
    Type: Application
    Filed: July 5, 2018
    Publication date: November 1, 2018
    Applicant: Micron Technology, Inc.
    Inventor: Durai Vishak Nirmal Ramaswamy
  • Publication number: 20180308537
    Abstract: A field effect transistor construction includes a semiconductive channel core. A source/drain region is at opposite ends of the channel core. A gate is proximate a periphery of the channel core. A gate insulator is between the gate and the channel core. The gate insulator has local regions radially there-through that have different capacitance at different circumferential locations relative to the channel core periphery. Additional constructions, and methods, are disclosed.
    Type: Application
    Filed: June 19, 2018
    Publication date: October 25, 2018
    Applicant: Micron Technology, Inc.
    Inventors: Kamal M. Karda, Chandra Mouli, Durai Vishak Nirmal Ramaswamy, F. Daniel Gealy
  • Publication number: 20180294271
    Abstract: A memory cell includes a first electrode and a second electrode. A select device and a programmable device are in series with each other between the first and second electrodes. The select device is proximate and electrically coupled to the first electrode. The programmable device is proximate and electrically coupled to the second electrode. The programmable device includes a radially inner electrode having radially outer sidewalls. Ferroelectric material is radially outward of the outer sidewalls of the inner electrode. A radially outer electrode is radially outward of the ferroelectric material. One of the outer electrode or the inner electrode is electrically coupled to the select device. The other of the outer electrode and the inner electrode is electrically coupled to the second electrode. Arrays of memory cells are disclosed.
    Type: Application
    Filed: June 13, 2018
    Publication date: October 11, 2018
    Applicant: Micron Technology, Inc.
    Inventors: Durai Vishak Nirmal Ramaswamy, Wayne Kinney, Marco Domenico Tiburzi
  • Patent number: 10090462
    Abstract: Electronic apparatus, systems, and methods can include a resistive memory cell having a structured as an operably variable resistance region between two electrodes and a metallic barrier disposed in a region between the dielectric and one of the two electrodes. The metallic barrier can have a structure and a material composition to provide oxygen diffusivity above a first threshold during program or erase operations of the resistive memory cell and oxygen diffusivity below a second threshold during a retention state of the resistive memory cell. Additional apparatus, systems, and methods are disclosed.
    Type: Grant
    Filed: December 7, 2015
    Date of Patent: October 2, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Durai Vishak Nirmal Ramaswamy, Lei Bi, Beth R. Cook, Dale W. Collins
  • Publication number: 20180277602
    Abstract: A method of forming an array of memory cells includes forming lines of covering material that are elevationally over and along lines of spaced sense line contacts. Longitudinal orientation of the lines of covering material is used in forming lines comprising programmable material and outer electrode material that are between and along the lines of covering material. The covering material is removed over the spaced sense line contacts and the spaced sense line contacts are exposed. Access lines are formed. Sense lines are formed that are electrically coupled to the spaced sense line contacts. The sense lines are angled relative to the lines of spaced sense line contacts and relative to the access lines. Other embodiments, including structure independent of method, are disclosed.
    Type: Application
    Filed: May 23, 2018
    Publication date: September 27, 2018
    Applicant: Micron Technology, Inc.
    Inventors: Scott E. Sills, Durai Vishak Nirmal Ramaswamy
  • Patent number: 10083732
    Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A cell may be written with a value that is intended to convey a different logic state than may typically be associated with the value. For example, a cell that has stored a charge associated with one logic state for a time period may be re-written to store a different charge, and the re-written cell may still be read to have the originally stored logic state. An indicator may be stored in a latch to indicate whether the logic state currently stored by the cell is the intended logic state of the cell. A cell may, for example, be re-written with an opposite value periodically, based on the occurrence of an event, or based on a determination that the cell has stored one value (or charge) for a certain time period.
    Type: Grant
    Filed: July 10, 2017
    Date of Patent: September 25, 2018
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Alessandro Calderoni, Durai Vishak Nirmal Ramaswamy, Kirk Prall, Ferdinando Bedeschi
  • Patent number: 10084084
    Abstract: A ferroelectric field effect transistor comprises a semiconductive channel comprising opposing sidewalls and an elevationally outermost top. A source/drain region is at opposite ends of the channel. A gate construction of the transistor comprises inner dielectric extending along the channel top and laterally along the channel sidewalls. Inner conductive material is elevationally and laterally outward of the inner dielectric and extends along the channel top and laterally along the channel sidewalls. Outer ferroelectric material is elevationally outward of the inner conductive material and extends along the channel top. Outer conductive material is elevationally outward of the outer ferroelectric material and extends along the channel. Other constructions and methods are disclosed.
    Type: Grant
    Filed: August 15, 2017
    Date of Patent: September 25, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Durai Vishak Nirmal Ramaswamy, Kirk D. Prall
  • Publication number: 20180269283
    Abstract: Some embodiments include an integrated memory having an array of capacitors. The array has edges. The capacitors along the edges are edge capacitors, and the other capacitors are internal capacitors. The edge capacitors have inner edges facing toward the internal capacitors, and have outer edges in opposing relation to the inner edges. An insulative beam extends laterally between the capacitors. The insulative beam is along upper regions of the capacitors. First void regions are under the insulative beam, along lower regions of the internal capacitors, and along the inner edges of the edge capacitors. Peripheral extensions of the insulative beam extend laterally outward of the edge capacitors, and second void regions are under the peripheral extensions and along the outer edges of the edge capacitors. Some embodiments included integrated assemblies having two or more memory array decks stacked on atop another. Some embodiments include methods of forming memory arrays.
    Type: Application
    Filed: May 17, 2018
    Publication date: September 20, 2018
    Applicant: Micron Technology, Inc.
    Inventor: Durai Vishak Nirmal Ramaswamy
  • Patent number: 10074662
    Abstract: A memory cell includes a first electrode and a second electrode. A select device and a programmable device are in series with each other between the first and second electrodes. The select device is proximate and electrically coupled to the first electrode. The programmable device is proximate and electrically coupled to the second electrode. The programmable device includes a radially inner electrode having radially outer sidewalls. Ferroelectric material is radially outward of the outer sidewalls of the inner electrode. A radially outer electrode is radially outward of the ferroelectric material. One of the outer electrode or the inner electrode is electrically coupled to the select device. The other of the outer electrode and the inner electrode is electrically coupled to the second electrode. Arrays of memory cells are disclosed.
    Type: Grant
    Filed: September 26, 2016
    Date of Patent: September 11, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Durai Vishak Nirmal Ramaswamy, Wayne Kinney, Marco Domenico Tiburzi
  • Patent number: 10062426
    Abstract: A field effect transistor construction includes a semiconductive channel core. A source/drain region is at opposite ends of the channel core. A gate is proximate a periphery of the channel core. A gate insulator is between the gate and the channel core. The gate insulator has local regions radially there-through that have different capacitance at different circumferential locations relative to the channel core periphery. Additional constructions, and methods, are disclosed.
    Type: Grant
    Filed: April 24, 2014
    Date of Patent: August 28, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Kamal M. Karda, Chandra Mouli, Durai Vishak Nirmal Ramaswamy, F. Daniel Gealy
  • Patent number: 10062745
    Abstract: A method of forming an array of capacitors comprises forming elevationally-extending and longitudinally-elongated capacitor electrode lines over a substrate. Individual of the capacitor electrode lines are common to and a shared one of two capacitor electrodes of individual capacitors longitudinally along a line of capacitors being formed. A capacitor insulator is formed over a pair of laterally-opposing sides of and longitudinally along individual of the capacitor electrode lines. An elevationally-extending conductive line is formed over the capacitor insulator longitudinally along one of the laterally-opposing sides of the individual capacitor electrode lines. The conductive line is cut laterally through to form spaced individual other of the two capacitor electrodes of the individual capacitors. Other methods are disclosed, including structures independent of method of manufacture.
    Type: Grant
    Filed: January 9, 2017
    Date of Patent: August 28, 2018
    Assignee: Micron Technology, Inc.
    Inventor: Durai Vishak Nirmal Ramaswamy
  • Patent number: 10026836
    Abstract: Some embodiments include transistor constructions having a first insulative structure lining a recess within a base. A first conductive structure lines an interior of the first insulative structure, and a ferroelectric structure lines an interior of the first conductive structure. A second conductive structure is within a lower region of the ferroelectric structure, and the second conductive structure has an uppermost surface beneath an uppermost surface of the first conductive structure. A second insulative structure is over the second conductive structure and within the ferroelectric structure. A pair of source/drain regions are adjacent an upper region of the first insulative structure and are on opposing sides of the first insulative structure from one another.
    Type: Grant
    Filed: February 13, 2017
    Date of Patent: July 17, 2018
    Assignee: Micron Technology, Inc.
    Inventor: Durai Vishak Nirmal Ramaswamy
  • Publication number: 20180197870
    Abstract: A memory cell comprises a capacitor having a first conductive capacitor electrode having laterally-spaced walls that individually have a top surface. A second conductive capacitor electrode is laterally between the walls of the first capacitor electrode, and comprises a portion above the first capacitor electrode. Ferroelectric material is laterally between the walls of the first capacitor electrode and laterally between the second capacitor electrode and the first capacitor electrode. The capacitor comprises an intrinsic current leakage path from one of the first and second capacitor electrodes to the other through the ferroelectric material. A parallel current leakage path is between an elevationally-inner surface of the portion of the second capacitor electrode that is above the first capacitor electrode and at least one of the individual top surfaces of the laterally-spaced walls of the first capacitor electrode.
    Type: Application
    Filed: January 12, 2017
    Publication date: July 12, 2018
    Inventors: Muralikrishnan Balakrishnan, Beth R. Cook, Durai Vishak Nirmal Ramaswamy
  • Publication number: 20180195049
    Abstract: A method of forming a tier of an array of memory cells within an array area, the memory cells individually comprising a capacitor and an elevationally-extending transistor, the method comprising using two, and only two, sacrificial masking steps within the array area of the tier in forming the memory cells. Other methods are disclosed, as are structures independent of method of fabrication.
    Type: Application
    Filed: November 21, 2017
    Publication date: July 12, 2018
    Inventor: Durai Vishak Nirmal Ramaswamy
  • Publication number: 20180197949
    Abstract: Some embodiments include an integrated memory having an array of capacitors. The array has edges. The capacitors along the edges are edge capacitors, and the other capacitors are internal capacitors. The edge capacitors have inner edges facing toward the internal capacitors, and have outer edges in opposing relation to the inner edges. An insulative beam extends laterally between the capacitors. The insulative beam is along upper regions of the capacitors. First void regions are under the insulative beam, along lower regions of the internal capacitors, and along the inner edges of the edge capacitors. Peripheral extensions of the insulative beam extend laterally outward of the edge capacitors, and second void regions are under the peripheral extensions and along the outer edges of the edge capacitors. Some embodiments included integrated assemblies having two or more memory array decks stacked on atop another. Some embodiments include methods of forming memory arrays.
    Type: Application
    Filed: January 6, 2017
    Publication date: July 12, 2018
    Inventor: Durai Vishak Nirmal Ramaswamy
  • Publication number: 20180197942
    Abstract: A method of forming an array of capacitors comprises forming elevationally-extending and longitudinally-elongated capacitor electrode lines over a substrate. Individual of the capacitor electrode lines are common to and a shared one of two capacitor electrodes of individual capacitors longitudinally along a line of capacitors being formed. A capacitor insulator is formed over a pair of laterally-opposing sides of and longitudinally along individual of the capacitor electrode lines. An elevationally-extending conductive line is formed over the capacitor insulator longitudinally along one of the laterally-opposing sides of the individual capacitor electrode lines. The conductive line is cut laterally through to form spaced individual other of the two capacitor electrodes of the individual capacitors. Other methods are disclosed, including structures independent of method of manufacture.
    Type: Application
    Filed: January 9, 2017
    Publication date: July 12, 2018
    Inventor: Durai Vishak Nirmal Ramaswamy
  • Publication number: 20180197869
    Abstract: A method of forming an array comprising pairs of vertically opposed capacitors comprises forming a conductive lining in individual capacitor openings in support material. An elevational mid-portion of individual of the conductive linings is removed to form an upper capacitor electrode lining and a lower capacitor electrode lining that are elevationally separate and spaced from one another in the individual capacitor openings. A capacitor insulator is formed laterally outward of the upper and lower capacitor electrode linings. Conductive material is formed laterally outward of the capacitor insulator to comprise a shared capacitor electrode that is shared by vertically opposed capacitors in individual of the pairs of vertically opposed capacitors. Other methods and structure independent of method of manufacture are disclosed.
    Type: Application
    Filed: March 6, 2018
    Publication date: July 12, 2018
    Applicant: Micron Technology, Inc.
    Inventors: Ashonita A. Chavan, Durai Vishak Nirmal Ramaswamy
  • Publication number: 20180197862
    Abstract: A method of forming an array of capacitors and access transistors there-above comprises forming access transistor trenches partially into insulative material. The trenches individually comprise longitudinally-spaced masked portions and longitudinally-spaced openings in the trenches longitudinally between the masked portions. The trench openings have walls therein extending longitudinally in and along the individual trench openings against laterally-opposing sides of the trenches. At least some of the insulative material that is under the trench openings is removed through bases of the trench openings between the walls and the masked portions to form individual capacitor openings in the insulative material that is lower than the walls. Individual capacitors are formed in the individual capacitor openings. A line of access transistors is formed in the individual trenches. The line of access transistors electrically couples to the individual capacitors that are along that line.
    Type: Application
    Filed: November 20, 2017
    Publication date: July 12, 2018
    Inventors: Scott E. Sills, Durai Vishak Nirmal Ramaswamy