Patents by Inventor Durai Vishak Nirmal Ramaswamy

Durai Vishak Nirmal Ramaswamy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11706929
    Abstract: A memory cell includes a select device and a capacitor electrically coupled in series with the select device. The capacitor includes two conductive capacitor electrodes having ferroelectric material there-between. The capacitor has an intrinsic current leakage path from one of the capacitor electrodes to the other through the ferroelectric material. There is a parallel current leakage path from the one capacitor electrode to the other. The parallel current leakage path is circuit-parallel the intrinsic path and of lower total resistance than the intrinsic path. Other aspects are disclosed.
    Type: Grant
    Filed: December 23, 2021
    Date of Patent: July 18, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Kamal M. Karda, Qian Tao, Durai Vishak Nirmal Ramaswamy, Haitao Liu, Kirk D. Prall, Ashonita Chavan
  • Patent number: 11695077
    Abstract: A transistor comprises a pair of source/drain regions having a channel there-between. A transistor gate construction is operatively proximate the channel. The channel comprises Si1-yGey, where “y” is from 0 to 0.6. At least a portion of each of the source/drain regions comprises Si1-xGex, where “x” is from 0.5 to 1. Other embodiments, including methods, are disclosed.
    Type: Grant
    Filed: February 17, 2021
    Date of Patent: July 4, 2023
    Assignee: Micron Technology, Inc.
    Inventor: Durai Vishak Nirmal Ramaswamy
  • Patent number: 11688450
    Abstract: Some embodiments include apparatuses in which one of such apparatus includes a first memory cell including a first transistor having a first channel region coupled between a data line and a conductive region, and a first charge storage structure located between the first data line and the conductive region, and a second transistor having a second channel region coupled to and located between the first data line and the first charge storage structure; a second memory cell including a third transistor having a third channel region coupled between a second data line and the conductive region, and a second charge storage structure located between the second data line and the conductive region, and a fourth transistor having a fourth channel region coupled to and located between the second data line and the second charge storage structure; a conductive line forming a gate of each of the first, second, third, and fourth transistors; and a conductive structure located between the first and second charge storage stru
    Type: Grant
    Filed: February 26, 2021
    Date of Patent: June 27, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Kamal M. Karda, Haitao Liu, Karthik Sarpatwari, Durai Vishak Nirmal Ramaswamy, Alessandro Calderoni, Richard E Fackenthal, Duane R. Mills
  • Patent number: 11676768
    Abstract: Some embodiments include an apparatus having horizontally-spaced bottom electrodes supported by a supporting structure. Leaker device material is directly against the bottom electrodes. Insulative material is over the bottom electrodes, and upper electrodes are over the insulative material. Plate material extends across the upper electrodes and couples the upper electrodes to one another. The plate material is directly against the leaker device material. The leaker device material electrically couples the bottom electrodes to the plate material, and may be configured to discharge at least a portion of excess charge from the bottom electrodes to the plate material. Some embodiments include methods of forming apparatuses which include capacitors having bottom electrodes and top electrodes, with the top electrodes being electrically coupled to one another through a conductive plate. Leaker devices are formed to electrically couple the bottom electrodes to the conductive plate.
    Type: Grant
    Filed: July 14, 2022
    Date of Patent: June 13, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Ashonita A. Chavan, Beth R. Cook, Manuj Nahar, Durai Vishak Nirmal Ramaswamy
  • Patent number: 11665880
    Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a substrate, a conductive plate located over the substrate to couple a ground connection, a data line located between the substrate and the conductive plate, a memory cell, and a conductive line. The memory cell includes a first transistor and a second transistor. The first transistor includes a first region electrically coupled between the data line and the conductive plate, and a charge storage structure electrically separated from the first region. The second transistor includes a second region electrically coupled to the charge storage structure and the data line. The conductive line is electrically separated from the first and second regions and spans across part of the first region of the first transistor and part of the second region of the second transistor and forming a gate of the first and second transistors.
    Type: Grant
    Filed: August 26, 2020
    Date of Patent: May 30, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Kamal M. Karda, Karthik Sarpatwari, Haitao Liu, Durai Vishak Nirmal Ramaswamy
  • Patent number: 11658246
    Abstract: A device comprises a vertical transistor. The vertical transistor comprises a pillar structure, at least one gate electrode, and a dielectric material. The pillar structure comprises a source region, a drain region, and a channel region. The source region and the drain region each individually comprise at least one electrically conductive material configured to inhibit hydrogen permeation therethrough. The channel region comprises a semiconductive material vertically between the source region and the drain region. The at least one gate electrode laterally neighbors the channel region of the semiconductive structure. The dielectric material is laterally between the semiconductive structure and the at least one gate electrode. Additional devices, and related electronic systems and methods are also disclosed.
    Type: Grant
    Filed: October 8, 2019
    Date of Patent: May 23, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Kamal M. Karda, Ramanathan Gandhi, Yi Fang Lee, Haitao Liu, Durai Vishak Nirmal Ramaswamy, Scott E. Sills
  • Patent number: 11653489
    Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a conductive region, a first data line, a second data line, a first memory cell coupled to the first data line and the conductive region, a second memory cell coupled to the second data line and the conductive region, a conductive structure, and a conductive line. The first memory cell includes a first transistor coupled to a second transistor, the first transistor including a first charge storage structure. The second memory cell includes a third transistor coupled to a fourth transistor, the third transistor including a second charge storage structure. The conductive structure is located between and electrically separated from the first and second charge storage structures. The conductive line forms a gate of each of the first, second, third, and fourth transistors.
    Type: Grant
    Filed: August 26, 2020
    Date of Patent: May 16, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Kamal M. Karda, Haitao Liu, Karthik Sarpatwari, Durai Vishak Nirmal Ramaswamy
  • Publication number: 20230132576
    Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a memory cell including a first transistor, a second transistor, and a dielectric structure formed in a trench. The first transistor includes a first channel region, and a charge storage structure separated from the first channel region. The second transistor includes a second channel region formed over the charge storage structure. The dielectric structure includes a first dielectric portion formed on a first sidewall of the trench, and a second dielectric portion formed on a second sidewall of the trench. The charge storage structure is between and adjacent the first and second dielectric portions.
    Type: Application
    Filed: October 29, 2021
    Publication date: May 4, 2023
    Inventors: Durai Vishak Nirmal Ramaswamy, Kamal M. Karda
  • Publication number: 20230138322
    Abstract: Some embodiments include apparatuses and methods forming the apparatuses. One of the apparatuses includes a first memory cell including a first transistor including a first channel region and a first charge storage structure, and a second transistor including a second channel region formed over the charge storage structure; a second memory cell adjacent the first memory cell, the second memory cell including a third transistor including a third channel region and a second charge storage structure, and a fourth transistor including a fourth channel region formed over the second charge storage structure; a first access line adjacent a side of the first memory cell; a second access line adjacent a side of the second memory cell; a first dielectric material adjacent the first channel region; a second dielectric material adjacent the third channel region; and a conductive structure between the first and second dielectric materials and adjacent the first and second dielectric materials.
    Type: Application
    Filed: October 29, 2021
    Publication date: May 4, 2023
    Inventors: Kamal M. Karda, Richard E. Fackenthal, Durai Vishak Nirmal Ramaswamy
  • Publication number: 20230121892
    Abstract: A method used in forming an electronic component comprising conductive material and ferroelectric material comprises forming a non-ferroelectric metal oxide-comprising insulator material over a substrate. A composite stack comprising at least two different composition non-ferroelectric metal oxides is formed over the substrate. The composite stack has an overall conductivity of at least 1×102 Siemens/cm. The composite stack is used to render the non-ferroelectric metal oxide-comprising insulator material to be ferroelectric. Conductive material is formed over the composite stack and the insulator material. Ferroelectric capacitors and ferroelectric field effect transistors independent of method of manufacture are also disclosed.
    Type: Application
    Filed: November 30, 2022
    Publication date: April 20, 2023
    Applicant: Micron Technology, Inc.
    Inventors: Ashonita A. Chavan, Durai Vishak Nirmal Ramaswamy
  • Patent number: 11631453
    Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes multiple levels of two-transistor (2T) memory cells vertically arranged above a substrate. Each 2T memory cell includes a charge storage transistor having a gate, a write transistor having a gate, a vertically extending access line, and a single bit line pair. The source or drain region of the write transistor is directly coupled to a charge storage structure of the charge storage transistor. The vertically extending access line is coupled to gates of both the charge storage transistor and the write transistor of 2T memory cells in multiple respective levels of the multiple vertically arranged levels. The vertically extending access line and the single bit line pair are used for both write operations and read operations of each of the 2T memory cells to which they are coupled.
    Type: Grant
    Filed: December 8, 2021
    Date of Patent: April 18, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Kamal M. Karda, Haitao Liu, Karthik Sarpatwari, Durai Vishak Nirmal Ramaswamy
  • Patent number: 11616073
    Abstract: Some embodiments include apparatuses and methods forming the apparatuses. One of the apparatuses includes a first transistor including a first channel region, and a charge storage structure separated from the first channel region; a second transistor including a second channel region formed over the charge storage structure; and a data line formed over and contacting the first channel region and the second channel region, the data line including a portion adjacent the first channel region and separated from the first channel region by a dielectric material.
    Type: Grant
    Filed: October 29, 2021
    Date of Patent: March 28, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Kamal M. Karda, Eric S. Carman, Karthik Sarpatwari, Durai Vishak Nirmal Ramaswamy, Richard E Fackenthal, Haitao Liu
  • Publication number: 20230081634
    Abstract: A transistor comprises a first conductive contact, a heterogeneous channel comprising at least one oxide semiconductor material over the first conductive contact, a second conductive contact over the heterogeneous channel, and a gate electrode laterally neighboring the heterogeneous channel. A device, a method of forming a device, a memory device, and an electronic system are also described.
    Type: Application
    Filed: October 27, 2022
    Publication date: March 16, 2023
    Inventors: Scott E. Sills, Ramanathan Gandhi, Durai Vishak Nirmal Ramaswamy, Yi Fang Lee, Kamal M. Karda
  • Patent number: 11605723
    Abstract: Some embodiments include integrated memory having an array of access transistors. Each access transistor includes an active region which has a first source/drain region, a second source/drain region and a channel region. The active regions of the access transistors include semiconductor material having elements selected from Groups 13 and 16 of the periodic table. First conductive structures extend along rows of the array and have gating segments adjacent the channel regions of the access transistors. Heterogenous insulative regions are between the gating segments and the channel regions. Second conductive structures extend along columns of the array, and are electrically coupled with the first source/drain regions. Storage-elements are electrically coupled with the second source/drain regions. Some embodiments include a transistor having a semiconductor oxide channel material. A conductive gate material is adjacent to the channel material.
    Type: Grant
    Filed: July 28, 2020
    Date of Patent: March 14, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Scott E. Sills, Durai Vishak Nirmal Ramaswamy
  • Patent number: 11600691
    Abstract: A memory cell comprises a capacitor having a first conductive capacitor electrode having laterally-spaced walls that individually have a top surface. A second conductive capacitor electrode is laterally between the walls of the first capacitor electrode, and comprises a portion above the first capacitor electrode. Ferroelectric material is laterally between the walls of the first capacitor electrode and laterally between the second capacitor electrode and the first capacitor electrode. The capacitor comprises an intrinsic current leakage path from one of the first and second capacitor electrodes to the other through the ferroelectric material. A parallel current leakage path is between an elevationally-inner surface of the portion of the second capacitor electrode that is above the first capacitor electrode and at least one of the individual top surfaces of the laterally-spaced walls of the first capacitor electrode.
    Type: Grant
    Filed: December 17, 2020
    Date of Patent: March 7, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Muralikrishnan Balakrishnan, Beth R. Cook, Durai Vishak Nirmal Ramaswamy
  • Patent number: 11581319
    Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a memory cell, first, second, and third data lines, and first and second access lines. Each of the first, second, and third data lines includes a length extending in a first direction. Each of the first and second access lines includes a length extending in a second direction. The memory cell includes a first transistor including a charge storage structure, and a first channel region electrically separated from the charge storage structure, and a second transistor including a second channel region electrically coupled to the charge storage structure. The first data line is electrically coupled to the first channel region. The second data line is electrically coupled to the first channel region. The third data line is electrically coupled to the second channel region, the second channel region being between the charge storage structure and the third data line.
    Type: Grant
    Filed: January 11, 2021
    Date of Patent: February 14, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Srinivas Pulugurtha, Durai Vishak Nirmal Ramaswamy
  • Publication number: 20230041784
    Abstract: Some embodiments include a ferroelectric transistor having a conductive gate structure, a first ring extending around the conductive gate structure and a second ring extending around the first ring. The first ring includes ferroelectric material. The second ring includes insulative material. A mass of channel material is outward of the second ring. Some embodiments include integrated assemblies and methods of forming integrated assemblies.
    Type: Application
    Filed: March 16, 2022
    Publication date: February 9, 2023
    Applicant: Micron Technology, Inc.
    Inventors: Durai Vishak Nirmal Ramaswamy, Kamal M. Karda
  • Publication number: 20230030364
    Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a memory cell, first, second, and third data lines, and first and second access lines. Each of the first, second, and third data lines includes a length extending in a first direction. Each of the first and second access lines includes a length extending in a second direction. The memory cell includes a first transistor including a charge storage structure, and a first channel region electrically separated from the charge storage structure, and a second transistor including a second channel region electrically coupled to the charge storage structure. The first data line is electrically coupled to the first channel region. The second data line is electrically coupled to the first channel region. The third data line is electrically coupled to the second channel region, the second channel region being between the charge storage structure and the third data line.
    Type: Application
    Filed: October 6, 2022
    Publication date: February 2, 2023
    Inventors: Srinivas Pulugurtha, Durai Vishak Nirmal Ramaswamy
  • Publication number: 20230031904
    Abstract: Some embodiments include apparatuses and methods of operating such apparatuses. One of such apparatuses includes a data line, a conductive region, and a memory cell including a first transistor and a second transistor. The first transistor includes a first channel region coupled to the data line and the conductive region, a charge storage structure, and a first gate. The second transistor includes a second channel region coupled to the data line and the charge storage structure, and a second gate. The first gate is electrically separated from the second gate and opposite from the second gate in a direction from the first channel region to the second channel region.
    Type: Application
    Filed: July 29, 2021
    Publication date: February 2, 2023
    Inventors: Eric S. Carman, Durai Vishak Nirmal Ramaswamy, Richard E Fackenthal, Kamal M. Karda, Karthik Sarpatwari, Haitao Liu, Duane R. Mills, Christian Caillat
  • Publication number: 20230030585
    Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a first data line located in a first level of the apparatus; a second data line located in a second level of the apparatus; a first memory cell located in a third level of the apparatus between the first and second levels, the first memory cell including a first transistor coupled to the first data line, and a second transistor coupled between the first data line and a charge storage structure of the first transistor; and a second memory cell located in a fourth level of the apparatus between the first and second levels, the second memory cell including a third transistor coupled to the second data line, and a fourth transistor coupled between the second data line and a charge storage structure of the third transistor, the first transistor coupled in series with the third transistor between the first and second data lines.
    Type: Application
    Filed: October 17, 2022
    Publication date: February 2, 2023
    Inventors: Karthik Sarpatwari, Kamal M. Karda, Durai Vishak Nirmal Ramaswamy, Haitao Liu