Patents by Inventor Durai Vishak Nirmal Ramaswamy

Durai Vishak Nirmal Ramaswamy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210313339
    Abstract: A method of forming a ferroelectric memory cell. The method comprises forming an electrode material exhibiting a desired dominant crystallographic orientation. A hafnium-based material is formed over the electrode material and the hafnium-based material is crystallized to induce formation of a ferroelectric material having a desired crystallographic orientation. Additional methods are also described, as are semiconductor device structures including the ferroelectric material.
    Type: Application
    Filed: June 14, 2021
    Publication date: October 7, 2021
    Applicant: Micron Technology, Inc.
    Inventors: Qian Tao, Matthew N. Rocklein, Beth R. Cook, Durai Vishak Nirmal Ramaswamy
  • Patent number: 11139396
    Abstract: A device comprises a first conductive line and a vertical transistor over the first conductive line. The vertical transistor comprises a gate electrode, a gate dielectric material overlying sides of the gate electrode, and a channel region on sides of the gate dielectric material, the gate dielectric material located between the channel region and the gate electrode. The device further comprises a second conductive line overlying a conductive contact of the at least one vertical transistor. Related devices and methods of forming the devices are also disclosed.
    Type: Grant
    Filed: October 8, 2019
    Date of Patent: October 5, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Kamal M. Karda, Durai Vishak Nirmal Ramaswamy, Haitao Liu
  • Patent number: 11127745
    Abstract: A method of forming an apparatus comprises forming a first metal nitride material over an upper surface of a conductive material within an opening extending through at least one dielectric material through a non-conformal deposition process. A second metal nitride material is formed over an upper surface of the first metal nitride material and side surfaces of the at least one dielectric material partially defining boundaries of the opening through a conformal deposition process. A conductive structure is formed over surfaces of the second metal nitride material within the opening. Apparatuses and electronic systems are also described.
    Type: Grant
    Filed: June 19, 2020
    Date of Patent: September 21, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Kentaro Ishii, Yongjun J. Hu, Amirhasan Nourbakhsh, Durai Vishak Nirmal Ramaswamy, Christopher W. Petz, Luca Fumagalli
  • Patent number: 11121177
    Abstract: A method of forming an array of memory cells includes forming lines of covering material that are elevationally over and along lines of spaced sense line contacts. Longitudinal orientation of the lines of covering material is used in forming lines comprising programmable material and outer electrode material that are between and along the lines of covering material. The covering material is removed over the spaced sense line contacts and the spaced sense line contacts are exposed. Access lines are formed. Sense lines are formed that are electrically coupled to the spaced sense line contacts. The sense lines are angled relative to the lines of spaced sense line contacts and relative to the access lines. Other embodiments, including structure independent of method, are disclosed.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: September 14, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Scott E. Sills, Durai Vishak Nirmal Ramaswamy
  • Publication number: 20210280231
    Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A cell may be written with a value that is intended to convey a different logic state than may typically be associated with the value. For example, a cell that has stored a charge associated with one logic state for a time period may be re-written to store a different charge, and the re-written cell may still be read to have the originally stored logic state. An indicator may be stored in a latch to indicate whether the logic state currently stored by the cell is the intended logic state of the cell. A cell may, for example, be re-written with an opposite value periodically, based on the occurrence of an event, or based on a determination that the cell has stored one value (or charge) for a certain time period.
    Type: Application
    Filed: March 24, 2021
    Publication date: September 9, 2021
    Inventors: Alessandro Calderoni, Durai Vishak Nirmal Ramaswamy, Kirk Prall, Ferdinando Bedeschi
  • Publication number: 20210272965
    Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a memory cell, first, second, and third data lines, and first and second access lines. Each of the first, second, and third data lines includes a length extending in a first direction. Each of the first and second access lines includes a length extending in a second direction. The memory cell includes a first transistor including a charge storage structure, and a first channel region electrically separated from the charge storage structure, and a second transistor including a second channel region electrically coupled to the charge storage structure. The first data line is electrically coupled to the first channel region. The second data line is electrically coupled to the first channel region. The third data line is electrically coupled to the second channel region, the second channel region being between the charge storage structure and the third data line.
    Type: Application
    Filed: January 11, 2021
    Publication date: September 2, 2021
    Inventors: Srinivas Pulugurtha, Durai Vishak Nirmal Ramaswamy
  • Patent number: 11107724
    Abstract: Some embodiments include an integrated memory having an array of capacitors. The array has edges. The capacitors along the edges are edge capacitors, and the other capacitors are internal capacitors. The edge capacitors have inner edges facing toward the internal capacitors, and have outer edges in opposing relation to the inner edges. An insulative beam extends laterally between the capacitors. The insulative beam is along upper regions of the capacitors. First void regions are under the insulative beam, along lower regions of the internal capacitors, and along the inner edges of the edge capacitors. Peripheral extensions of the insulative beam extend laterally outward of the edge capacitors, and second void regions are under the peripheral extensions and along the outer edges of the edge capacitors. Some embodiments included integrated assemblies having two or more memory array decks stacked on atop another. Some embodiments include methods of forming memory arrays.
    Type: Grant
    Filed: August 17, 2020
    Date of Patent: August 31, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Durai Vishak Nirmal Ramaswamy
  • Patent number: 11107817
    Abstract: Some embodiments include an integrated assembly having a first semiconductor material between two regions of a second semiconductor material. The second semiconductor material is a different composition than the first semiconductor material. Hydrogen is diffused within the first and second semiconductor materials. The conductivity of the second semiconductor material increases in response to the hydrogen diffused therein to thereby create a structure having the second semiconductor material as source/drain regions, and having the first semiconductor material as a channel region between the source/drain regions. A transistor gate is adjacent the channel region and is configured to induce an electric field within the channel region. Some embodiments include methods of forming integrated assemblies.
    Type: Grant
    Filed: March 11, 2019
    Date of Patent: August 31, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Kamal M. Karda, Yi Fang Lee, Haitao Liu, Durai Vishak Nirmal Ramaswamy, Ramanathan Gandhi, Karthik Sarpatwari, Scott E. Sills, Sameer Chhajed
  • Patent number: 11101274
    Abstract: A ferroelectric capacitor comprises two conductive capacitor electrodes having ferroelectric material there-between. At least one of the capacitor electrodes comprise MxSiOy, where “M” is at least one of Ru, Ti, Ta, Co, Pt, Ir. Os, Mo, V, W, Sr, Re, Rh, Pd, La, Zn, In, Sn, and Nb. Other aspects, including method, are disclosed.
    Type: Grant
    Filed: December 5, 2019
    Date of Patent: August 24, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Clement Jacob, Vassil N. Antonov, Jaydeb Goswami, Albert Liao, Christopher W. Petz, Durai Vishak Nirmal Ramaswamy
  • Patent number: 11101271
    Abstract: A method of forming an array of cross point memory cells comprises using two, and only two, masking steps to collectively pattern within the array spaced lower first lines, spaced upper second lines which cross the first lines, and individual programmable devices between the first lines and the second lines where such cross that have an upwardly open generally U-shape vertical cross-section of programmable material laterally between immediately adjacent of the first lines beneath individual of the upper second lines. Arrays of cross point memory cells independent of method of manufacture are disclosed.
    Type: Grant
    Filed: January 20, 2020
    Date of Patent: August 24, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Durai Vishak Nirmal Ramaswamy
  • Publication number: 20210242221
    Abstract: Some embodiments include a ferroelectric transistor having an active region which includes a first source/drain region, a second source/drain region, and a body region between the first and second source/drain regions. The body region has a different semiconductor composition than at least one of the first and second source/drain regions to enable replenishment of carrier within the body region. An insulative material is along the body region. A ferroelectric material is along the insulative material. A conductive gate material is along the ferroelectric material.
    Type: Application
    Filed: April 20, 2021
    Publication date: August 5, 2021
    Applicant: Micron Technology, Inc.
    Inventors: Kamal M. Karda, Durai Vishak Nirmal Ramaswamy, Haitao Liu
  • Publication number: 20210242226
    Abstract: A memory array comprises vertically-alternating tiers of insulative material and memory cells, with the memory cells individually comprising a transistor comprising first and second source/drain regions having a channel region there-between and a gate operatively proximate the channel region. At least a portion of the channel region is horizontally-oriented for horizontal current flow in the portion between the first and second source/drain regions. A capacitor of the memory cell comprises first and second electrodes having a capacitor insulator there-between. The first electrode is electrically coupled to the first source/drain region. A horizontal longitudinally-elongated sense line is in individual of the memory-cell tiers. Individual of the second source/drain regions of individual of the transistors that are in the same memory-cell tier are electrically coupled to the horizontal longitudinally-elongated sense line in that individual tier of memory cells.
    Type: Application
    Filed: April 20, 2021
    Publication date: August 5, 2021
    Applicant: Micron Technology, Inc.
    Inventor: Durai Vishak Nirmal Ramaswamy
  • Patent number: 11068166
    Abstract: A hybrid memory device may include volatile and non-volatile memory cells on a single substrate, or die. The non-volatile memory cells may have ferroelectric capacitors and the volatile memory cells may have paraelectric or linear dielectric capacitors for their respective logic storage components. In some examples, the volatile memory cells may be used as a cache for the non-volatile memory cells. Or the non-volatile memory cells may be used as a back-up for the volatile memory cells. By placing both types of cells on a single die, rather than separate dies, various performance metrics may be improved, including those related to power consumption and operation speed.
    Type: Grant
    Filed: March 19, 2019
    Date of Patent: July 20, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Kevin J. Ryan, Kirk D. Prall, Durai Vishak Nirmal Ramaswamy, Robert Quinn
  • Patent number: 11063054
    Abstract: A method of forming an array comprising pairs of vertically opposed capacitors comprises forming a conductive lining in individual capacitor openings in support material. An elevational mid-portion of individual of the conductive linings is removed to form an upper capacitor electrode lining and a lower capacitor electrode lining that are elevationally separate and spaced from one another in the individual capacitor openings. A capacitor insulator is formed laterally outward of the upper and lower capacitor electrode linings. Conductive material is formed laterally outward of the capacitor insulator to comprise a shared capacitor electrode that is shared by vertically opposed capacitors in individual of the pairs of vertically opposed capacitors. Other methods and structure independent of method of manufacture are disclosed.
    Type: Grant
    Filed: September 25, 2019
    Date of Patent: July 13, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Ashonita A. Chavan, Durai Vishak Nirmal Ramaswamy
  • Patent number: 11049804
    Abstract: An array of memory cells individually comprising a capacitor and a transistor comprises, in a first level, alternating columns of digitlines and conductive shield lines. In a second level above the first level there are rows of transistor wordlines. In a third level above the second level there are rows and columns of capacitors. In a fourth level above the third level there are rows of transistor wordlines. In a fifth level above the fourth level there are alternating columns of digitlines and conductive shield lines. Other embodiments and aspects are disclosed, including method.
    Type: Grant
    Filed: August 26, 2020
    Date of Patent: June 29, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Durai Vishak Nirmal Ramaswamy
  • Patent number: 11043502
    Abstract: A method of forming a ferroelectric memory cell. The method comprises forming an electrode material exhibiting a desired dominant crystallographic orientation. A hafnium-based material is formed over the electrode material and the hafnium-based material is crystallized to induce formation of a ferroelectric material having a desired crystallographic orientation. Additional methods are also described, as are semiconductor device structures including the ferroelectric material.
    Type: Grant
    Filed: August 26, 2019
    Date of Patent: June 22, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Qian Tao, Matthew N. Rocklein, Beth R. Cook, Durai Vishak Nirmal Ramaswamy
  • Patent number: 11043260
    Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes multiple two-transistor (2T) memory cells. Each of the multiple 2T memory cells includes: a p-channel field effect transistor (PFET) including a charge storage node and a read channel portion, an n-channel field effect transistor (NFET) including a write channel portion that is directly coupled to the charge storage node of the PFET; a single bit line pair coupled to the read channel portion of the PFET; and a single access line overlapping at least part of each of the read channel portion and the write channel portion.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: June 22, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Kamal M. Karda, Haitao Liu, Karthik Sarpatwari, Durai Vishak Nirmal Ramaswamy
  • Publication number: 20210183951
    Abstract: Methods of forming a semiconductor device are disclosed. A method comprising forming a hybrid transistor supported by a substrate. Forming the hybrid transistor comprises forming a source including a first low bandgap high mobility material, and forming a channel including a high bandgap low mobility material coupled with the first low bandgap high mobility material. Forming the hybrid transistor further comprises forming a drain including a second low bandgap high mobility material coupled with the a high bandgap low mobility material, and forming a gate separated from the channel via a gate oxide material. Methods of forming a transistor are also disclosed.
    Type: Application
    Filed: February 23, 2021
    Publication date: June 17, 2021
    Inventors: Kamal M. Karda, Haitao Liu, Durai Vishak Nirmal Ramaswamy
  • Publication number: 20210183864
    Abstract: A transistor comprises semiconductor material that is generally L-shaped or generally mirror L-shaped in at least one straight-line vertical cross-section thereby having an elevationally-extending stem and a base extending horizontally from a lateral side of the stem above a bottom of the stem. The semiconductor material of the stem comprises an upper source/drain region and a channel region there-below. The transistor comprises at least one of (a) and (b), where (a): the semiconductor material of the stem comprises a lower source/drain region below the channel region, and (b): the semiconductor material of the base comprises a lower source/drain region. A gate is operatively laterally adjacent the channel region of the stem. Other embodiments are disclosed, including arrays of memory cells individually comprising a capacitor and an elevationally-extending transistor. Methods are disclosed.
    Type: Application
    Filed: February 9, 2021
    Publication date: June 17, 2021
    Applicant: Micron Technology, Inc.
    Inventor: Durai Vishak Nirmal Ramaswamy
  • Patent number: 11037942
    Abstract: A memory cell includes a first electrode and a second electrode. A select device and a programmable device are in series with each other between the first and second electrodes. The select device is proximate and electrically coupled to the first electrode. The programmable device is proximate and electrically coupled to the second electrode. The programmable device includes a radially inner electrode having radially outer sidewalls. Ferroelectric material is radially outward of the outer sidewalls of the inner electrode. A radially outer electrode is radially outward of the ferroelectric material. One of the outer electrode or the inner electrode is electrically coupled to the select device. The other of the outer electrode and the inner electrode is electrically coupled to the second electrode. Arrays of memory cells are disclosed.
    Type: Grant
    Filed: January 15, 2020
    Date of Patent: June 15, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Durai Vishak Nirmal Ramaswamy, Wayne Kinney, Marco Domenico Tiburzi