Abstract: A method of programming an MTJ includes selecting the MTJ and an access transistor coupled thereto. The gate of the selected access transistor is coupled to a selected word line (WL), which is raised to a first voltage, Vdd, and is then allowed to float. The first voltage and a second voltage, Vx, are respectively applied to a selected bit line (BL) coupled to the selected MTJ and a selected source line (SL) coupled to the selected access transistor, thereby driving a switching current through the selected MTJ from the selected BL to SL. Alternatively, the switching current may be reversed by applying 0 V and Vdd to the selected BL and SL, respectively. Moreover, the second voltage is applied to other BLs not coupled to the selected MTJ and the first voltage is applied to other SLs not coupled to the selected access transistor, thereby boosting the voltage of the floating WL to above the first voltage.

Abstract: A non-volatile memory system includes a first circuit and a second circuit both coupled to a magnetoresistance tunnel junction (MTJ) cell to substantially reduce the level of current flowing through the MTJ with rise in temperature, as experienced by the MTJ. The first circuit is operable to adjust a slope of a curve representing current as a function of temperature and the second circuit is operable to adjust a value of the current level through the MTJ to maintain current constant or to reduce current when the temperature increases. This way sufficient current is provided for the MTJ at different temperatures to prevent write failure, over programming, MTJ damage and waste of current.

Abstract: A method of programming an MTJ includes selecting the MTJ and an access transistor coupled thereto. The gate of the selected access transistor is coupled to a selected word line (WL), which is raised to a first voltage, Vdd, and is then allowed to float. The first voltage and a second voltage, Vx, are respectively applied to a selected bit line (BL) coupled to the selected MTJ and a selected source line (SL) coupled to the selected access transistor, thereby driving a switching current through the selected MTJ from the selected BL to SL. Alternatively, the switching current may be reversed by applying 0 V and Vdd to the selected BL and SL, respectively. Moreover, the second voltage is applied to other BLs not coupled to the selected MTJ and the first voltage is applied to other SLs not coupled to the selected access transistor, thereby boosting the voltage of the floating WL to above the first voltage.

Abstract: A spin-transfer torque magnetic random access memory (STTMRAM) cell is disclosed. The memory cell comprises a selected magnetic tunnel junction (MTJ) identified to be programmed; a first transistor having a first port, a second port and a gate, the first port of the first transistor coupled to the selected MTJ; a first neighboring MTJ coupled to the selected MTJ through the second port of the first transistor; a second transistor having a first port, a second port, and a gate, the first port of the second transistor coupled to the selected MTJ; a second neighboring MTJ coupled to the selected MTJ through the second port of the second transistor; a first bit/source line coupled to the second end of the selected MTJ; and a second bit/source line coupled to the second end of the first neighboring MTJ and the second end of the second neighboring MTJ.

Abstract: The present invention is directed to a memory subsystem including a plurality of memory banks, each of the memory banks including a plurality of memory cells arranged in rows and columns with word-lines connecting to the memory cells along a row direction and bit-lines connecting to the memory cells along a column direction; a sense amplifier module shared by the plurality of memory banks, the sense amplifier module including a plurality of sense amplifiers for sensing resistance of the memory cells; a plurality of memory buffer modules coupled to the sense amplifier module, each of the memory buffer modules including a plurality of memory buffers for storing data from the sense amplifiers; and an input/output (I/O) interface coupled to the memory buffer modules.

Abstract: A non-volatile memory system includes a first circuit and a second circuit both coupled to a magnetoresistance tunnel junction (MTJ) cell to substantially reduce the level of current flowing through the MTJ with rise in temperature, as experienced by the MTJ. The first circuit is operable to adjust a slope of a curve representing current as a function of temperature and the second circuit is operable to adjust a value of the current level through the MTJ to maintain current constant or to reduce current when the temperature increases. This way sufficient current is provided for the MTJ at different temperatures, to prevent write failure, over programming, MTJ damage and waste of current.

Abstract: A memory device having features of the present invention comprises a reprogrammable memory portion including therein a first plurality of magnetic tunnel junctions (MTJs) whose resistance is switchable; and a one-time-programmable (OTP) memory portion including therein a second plurality of MTJs whose resistance is switchable and a third plurality of MTJs whose resistance is fixed. Each MTJ of the first, second, and third plurality of MTJs includes a magnetic free layer having a magnetization direction substantially perpendicular to a layer plane thereof and a magnetic reference layer having a fixed magnetization direction substantially perpendicular to a layer plane thereof. The second plurality of MTJs represents one of two logical states and the third plurality of MTJs represents the other one of the two logical states.

Abstract: A non-volatile memory system includes a first circuit and a second circuit both coupled to a magnetoresistance tunnel junction (MTJ) cell to substantially reduce the level of current flowing through the MTJ with rise in temperature, as experienced by the MTJ. The first circuit is operable to adjust a slope of a curve representing current as a function of temperature and the second circuit is operable to adjust a value of the current level through the MTJ to maintain current constant or to reduce current when the temperature increases. This way sufficient current is provided for the MTJ at different temperatures, to prevent write failure, over programming, MTJ damage and waste of current.

Abstract: A method of programming an MTJ includes selecting an MTJ that is coupled to an access transistor at the drain of the access transistor. The gate of the access transistor is coupled to a selected word line (WL), the selected WL being substantially at a first voltage, Vdd; whereas the WLs that are not coupled to the MTJ are left to float. A second voltage, Vx, is applied to the unselected bit lines (BLs) and further applied to a source line (SL), the SL being coupled to the source of the access transistor. A third voltage, Vdd or 0 Volts, is applied to a selected BL, the selected BL being coupled the MTJ. The first voltage is applied to a SL, the SL being coupled to the source of the access transistor thereby causing the WL to boot above the first voltage.

Abstract: A method is disclosed for writing a magnetic tunnel junction (MTJ) of a magnetic memory array by switching a magnetic orientation associated with the MTJ from anti-parallel to parallel magnetic orientation. One end of the MTJ is coupled to a bit line while the opposite end of the MTJ is coupled to one end of an access transistor. The method includes the steps of applying a gate voltage that is approximately a sum of a first voltage and a second voltage to a gate of the access transistor with the second voltage being less than the first voltage; raising the bit line to the first voltage; and applying the second voltage to the opposite end of the access transistor to program the MTJ while maintaining a voltage difference between the gate and the one end of the access transistor to be less than or equal to the first voltage.

Abstract: A method of writing to magnetic tunnel junctions (MTJs) of a magnetic memory array includes storing in-coming data in a cache register, reading the present logic state of a first one of a set of at least two MTJs, the set of at least two MTJs including the first MTJ and a second MTJ. The in-coming data is to be written into the second MTJ. Further steps are storing the read logic state into a data register, swapping the contents of the data register and the cache register so that the cache register stores the read logic state and the data register stores the in-coming data, applying a first predetermined voltage level to the set of MTJs thereby causing the first MTJ to be over-written, applying a second predetermined voltage level to the set of MTJs, and storing the in-coming data into the second MTJ.

Abstract: MRAM devices that are switched by unipolar electron flow are described. Embodiments use arrays of cells that include a diode or transistor with a pMTJ. The switching between the high and low resistance states of the pMTJ is achieved by electron flow in the same direction, i.e. a unipolar flow. Embodiments of the invention include methods of operating unipolar MRAM devices that include a read step after a write step to verify the operation. Embodiments also include methods of operating unipolar MRAM devices that include an iterative stepped-voltage write process that includes a plurality of write-read steps that begin with a selected voltage for the write pulse for the first iteration and gradually increase the voltage for the write pulse for the next iteration until a successful read operation occurs.

Abstract: A method of programming an MTJ includes selecting an MTJ that is coupled to an access transistor at the drain of the access transistor. The gate of the access transistor is coupled to a selected word line (WL), the selected WL being substantially at a first voltage, Vdd; whereas the WLs that are not coupled to the MTJ are left to float. A second voltage, Vx, is applied to the unselected bit lines (BLs) and further applied to a source line (SL), the SL being coupled to the source of the access transistor. A third voltage, Vdd or 0 Volts, is applied to a selected BL, the selected BL being coupled the MTJ. The first voltage is applied to a SL, the SL being coupled to the source of the access transistor thereby causing the WL to boot above the first voltage.

Abstract: The present invention is directed to a magnetic random access memory (MRAM) comprising an MRAM die having a front side that includes therein a plurality of perpendicular magnetic tunnel junction (MTJ) memory elements and a back side; and a sheet of permanent magnet disposed in close proximity to the MRAM die with a sheet surface facing the front side or back side of the MRAM die. The sheet of permanent magnet has a permanent magnetization direction substantially perpendicular to the sheet surface facing the MRAM die and exerts a magnetic field that eliminate or minimize the offset field of the magnetic free layer. The MRAM die and the sheet of permanent magnet may be encapsulated by a package case. The MRAM may further comprise a soft magnetic shield disposed on a side of the MRAM die opposite the sheet of permanent magnet.

Abstract: The present invention is directed to a magnetic random access memory (MRAM) comprising an MRAM die having a front side that includes therein a plurality of perpendicular magnetic tunnel junction (MTJ) memory elements and a back side; and a sheet of permanent magnet disposed in close proximity to the MRAM die with a sheet surface facing the front side or back side of the MRAM die. The sheet of permanent magnet has a permanent magnetization direction substantially perpendicular to the sheet surface facing the MRAM die and exerts a magnetic field that eliminate or minimize the offset field of the magnetic free layer. The MRAM die and the sheet of permanent magnet may be encapsulated by a package case. The MRAM may further comprise a soft magnetic shield disposed on a side of the MRAM die opposite the sheet of permanent magnet.

Abstract: A method is disclosed for writing a magnetic tunnel junction (MTJ) of a magnetic memory array by switching a magnetic orientation associated with the MTJ from anti-parallel to parallel magnetic orientation. One end of the MTJ is coupled to a bit line while the opposite end of the MTJ is coupled to one end of an access transistor. The method includes the steps of applying a gate voltage that is approximately a sum of a first voltage and a second voltage to a gate of the access transistor with the second voltage being less than the first voltage; raising the bit line to the first voltage; and applying the second voltage to the opposite end of the access transistor to program the MTJ while maintaining a voltage difference between the gate and the one end of the access transistor to be less than or equal to the first voltage.

Abstract: A method of programming a MTJ includes selecting a MTJ that is coupled to an access transistor at the drain of the access transistor. The gate of the access transistor is coupled to a selected word line (WL), the selected WL is substantially at a first voltage, Vdd; whereas the WLs that are not coupled to the MTJ are left to float. A second voltage, Vx, is applied to the unselected bit lines (BLs) and further applied to a source line (SL), the SL being coupled to the source of the access transistor. A third voltage, Vdd or 0 Volts, is applied to a selected BL, the selected BL is coupled the MTJ. The first voltage is applied to a SL, the SL is coupled to the source of the access transistor thereby causing the WL to boot above the first voltage.

Abstract: MRAM devices that are switched by unipolar electron flow are described. Embodiments use arrays of cells that include a diode or transistor with a pMTJ. The switching between the high and low resistance states of the pMTJ is achieved by electron flow in the same direction, i.e. a unipolar flow. Embodiments of the invention include methods of operating unipolar MRAM devices that include a read step after a write step to verify the operation. Embodiments also include methods of operating unipolar MRAM devices that include an iterative stepped-voltage write process that includes a plurality of write-read steps that begin with a selected voltage for the write pulse for the first iteration and gradually increase the voltage for the write pulse for the next iteration until a successful read operation occurs.

Abstract: A testing method is described that applies a sequence external magnetic fields of varying strength to MRAM cells (such as those with MTJ memory elements) in chips or wafers to selectively screen out cells with low or high thermal stability factor. The coercivity (Hc) is used as a proxy for thermal stability factor (delta). In the various embodiments the sequence, direction and strength of the external magnetic fields is used to determine the high coercivity cells that are not switched by a normal field and the low coercivity cells that are switched by a selected low field. In some embodiment the MRAM's standard internal electric current can be used to switch the cells. Standard circuit-based resistance read operations can be used to determine the response of each cell to these magnetic fields and identify the abnormal high and low coercivity cells.

Abstract: A method of writing to a magnetic tunnel junction (MTJ) of a magnetic memory array includes an access transistor coupled to the MTJ for reading of and writing to the MTJ, where when the MTJ is written to, at times, by switching its magnetic orientation from an anti-parallel to a parallel magnetic orientation, a bit line that is coupled to one end of the MTJ is raised to Vcc and a voltage that is the sum of Vcc and Vx is applied to the gate of the access transistor, with Vx being approximately the voltage at an opposite end of the MTJ. Further, the voltage of a Source Line (SL), which is coupled to the MTJ using a first transistor of a write driver that is also coupled to the SL, is regulated such that SL remains sufficiently above 0 volts to avoid violation of Vgs exceeding Vcc where Vgs is the gate to source voltage of the access transistor.