Abstract: A general purpose interface tile of a first integrated circuit includes a plurality of micropads. A second integrated circuit may be stacked on the first integrated circuit such that signals from the second integrated circuit are communicated through the micropads and the interface tile to other circuitry on the first integrated circuit. Similarly, signals from the first integrated circuit are communicated through the interface tile and the micropads to the second integrated circuit. In the event that the first integrated circuit is a programmable logic device having a programmable interconnect structure, the interface tile is part of and hooks into the programmable interconnect structure and provides a general purpose mechanism for coupling signals from the second integrated circuit to the programmable interconnect structure and/or for coupling signals from the programmable interconnect structure to the second integrated circuit.

Abstract: A general purpose interface tile of a first integrated circuit includes a plurality of micropads. A second integrated circuit may be stacked on the first integrated circuit such that signals from the second integrated circuit are communicated through the micropads and the interface tile to other circuitry on the first integrated circuit. Similarly, signals from the first integrated circuit are communicated through the interface tile and the micropads to the second integrated circuit. In the event that the first integrated circuit is a programmable logic device having a programmable interconnect structure, the interface tile is part of and hooks into the programmable interconnect structure and provides a general purpose mechanism for coupling signals from the second integrated circuit to the programmable interconnect structure and/or for coupling signals from the programmable interconnect structure to the second integrated circuit.

Abstract: A method for selecting the state assignments of a complex programmable logic device (CPLD) to minimize power consumption. Within the CPLD, a plurality of macrocells are selected to store a corresponding plurality of state variables, wherein the number of macrocells is selected to be equal to the number of states. For each of the states, one of the macrocells is assigned to store a state variable having a first logic state, and the remaining macrocells are assigned to store state variables having a second logic state. The macrocells storing state variables having the second logic state exhibit a lower power consumption than the macrocell storing the state variable having the first logic state. In addition, each of the macrocells includes a plurality of wired logic gates, each being in a high-current state or a low-current state. The number of wired logic gates in the low-current state is maximized in the macrocells assigned to store the state variables having the second logic state.

Abstract: For an FPGA having a configuration memory arranged in rows and columns, a programmable address decoder with a counter selects the order in which columns of memory cells will be programmed and selects which columns of memory cells are programmed. The decoder structure addresses a particular column only when an address provided by the counter matches an address in the memory cells of the decoder for that column. Bitstreams intended for older devices can be successfully loaded into newer devices. Bitstreams developed for future devices with additional features can be loaded into devices with fewer features, and the additional features are not used. The counter can be set to count not in sequential order so that if extra columns are provided, a defective column of the FPGA controlled by a corresponding column of configuration memory cells can be bypassed.

Abstract: For antifuse programmable integrated circuit devices, in particular FPGA devices, the invention allows for alternative routing around antifuses which fail to program. The chip architecture includes wiring segments and antifuses which together allow for alternative routes around every antifuse in the event of failure of that antifuse. The method includes programming the device under control of a computer which can recalculate routes in the event of an antifuse which fails to program. Preferably the initial routing distributes unused wiring segments through the chip to be available for routing around a failed antifuse. When a failure occurs, the method includes determining an alternative route around every failed antifuse. The alternative route may be established directly after the antifuse has failed or after all initially selected antifuses have been programmed.