Patents by Inventor Edmund Blackshear
Edmund Blackshear has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11342697Abstract: A card, e.g. a printed circuit board (PCB), has one or more conductive layers and one or more non-conductive layers disposed and alternating upon one another to form a stack. One or more of the conductive layers has one or more wiring elements within the conductive layer. The PCB/card has one or more card edges. The PCB also has a plurality of dual-level pad structures on each of one or more of the card edges. The dual-level pad structures each have an upper level, a lower level, and two or more walls. The lower level is a conductive pad with conductive surface. At least one of the conductive pads electrically connects to one or more of the wiring elements and/or one or more vias. In each of the dual-level pad structures, the walls and upper level may be made of an electrically non-conductive, insulating, or dielectric material or may be covered with a conductive material that electrically connects to conductive surface.Type: GrantFiled: June 4, 2020Date of Patent: May 24, 2022Assignee: International Business Machines CorporationInventors: Paul W Coteus, Thomas Cipolla, Kyu-hyoun Kim, Edmund Blackshear
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Publication number: 20210384661Abstract: A card, e.g. a printed circuit board (PCB), has one or more conductive layers and one or more non-conductive layers disposed and alternating upon one another to form a stack. One or more of the conductive layers has one or more wiring elements within the conductive layer. The PCB/card has one or more card edges. The PCB also has a plurality of dual-level pad structures on each of one or more of the card edges. The dual-level pad structures each have an upper level, a lower level, and two or more walls. The lower level is a conductive pad with conductive surface. At least one of the conductive pads electrically connects to one or more of the wiring elements and/or one or more vias. In each of the dual-level pad structures, the walls and upper level may be made of an electrically non-conductive, insulating, or dielectric material or may be covered with a conductive material that electrically connects to conductive surface.Type: ApplicationFiled: June 4, 2020Publication date: December 9, 2021Inventors: Paul W. Coteus, Thomas Cipolla, Kyu-hyoun Kim, Edmund Blackshear
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Patent number: 10748852Abstract: Disclosed is a multi-chip module (MCM) with redundant chip-to-chip communication connection(s) to minimize the need to discard a chip-mounting layer due to defective signal traces. The MCM includes at least first and second chips mounted on the chip-mounting layer. The chip-mounting layer includes signal traces that are electrically connected between first and second links on the first and second chips, respectively, to form communication connections including at least one redundant communication connection. Instead of being directly connected to the chip-to-chip communication connections, first and second interfaces on the first and second chips are connected via first and second multiplexors, respectively, to selected ones of multiple chip-to-chip communication connections. By employing the multiplexors and the redundant chip-to-chip communication connection(s), chip-to-chip communication connection(s) with defective signal trace(s) can be bypassed.Type: GrantFiled: October 25, 2019Date of Patent: August 18, 2020Assignee: Marvell International Ltd.Inventors: Wolfgang Sauter, Mark W. Kuemerle, Edmund Blackshear
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Publication number: 20190363047Abstract: A panel assembly is configured with individual laminates to connect processors in parallel. The individual laminates may be arranged in rows and columns and separated by gaps on adjacent sides. This arrangement forms a placement area comprising a portion of the individual laminates resident in both neighboring rows and neighboring columns. A chip may be disposed on the substrate, the chip spanning the gaps to contact the portion of the individual laminates found in the placement area.Type: ApplicationFiled: May 24, 2018Publication date: November 28, 2019Applicant: GLOBALFOUNDRIES INC.Inventors: Edmund Blackshear, Eric W. Tremble, Wolfgang Sauter, David B. Stone
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Patent number: 9818682Abstract: A laminate substrate for receiving a semiconductor chip. Included are laminate layers stacked to form the laminate substrate, each laminate layer includes a core that includes particle-filled epoxy and a metallic layer on the core. At least one laminate layer has a radial cut through the metallic layer, the radial cut extending from a periphery of the at least one laminate layer towards a center of the at least one laminate layer. The radial cut cuts only through the metallic layer and does not cut through the core.Type: GrantFiled: December 3, 2014Date of Patent: November 14, 2017Assignee: International Business Machines CorporationInventors: Edmund Blackshear, Shidong Li
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Patent number: 9743526Abstract: A method of making a wiring board includes forming a first capacitor carrier layer with a first embedded chip capacitor, a first insulation layer disposed on an upper surface, a second insulation layer disposed on a lower surface, first upper and lower conductive vias in conductive contact with a first electrode, and second upper and lower conductive vias in conductive contact with a second electrode. The method also includes forming a second capacitor carrier layer similar to the first. The method further includes forming a bonded laminate comprising in sequence an upper insulation layer, the first capacitor carrier layer, a center insulation layer, the second capacitor carrier layer, and a lower insulation layer. The method also includes forming a through-hole through the laminate and forming a conductive coating within the through-hole to provide a conductive through-hole. A wiring board also includes the bonded laminate and the embedded capacitors.Type: GrantFiled: February 10, 2016Date of Patent: August 22, 2017Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, SHINKO ELECTRIC INDUSTRIES CO. LTDInventors: Edmund Blackshear, Keiichi Hirabayashi, Yoichi Miyazawa, Brian W. Quinlan, Junji Sato
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Publication number: 20170231094Abstract: A method of making a wiring board includes forming a first capacitor carrier layer with a first embedded chip capacitor, a first insulation layer disposed on an upper surface, a second insulation layer disposed on a lower surface, first upper and lower conductive vias in conductive contact with a first electrode, and second upper and lower conductive vias in conductive contact with a second electrode. The method also includes forming a second capacitor carrier layer similar to the first. The method further includes forming a bonded laminate comprising in sequence an upper insulation layer, the first capacitor carrier layer, a center insulation layer, the second capacitor carrier layer, and a lower insulation layer. The method also includes forming a through-hole through the laminate and forming a conductive coating within the through-hole to provide a conductive through-hole. A wiring board also includes the bonded laminate and the embedded capacitors.Type: ApplicationFiled: February 10, 2016Publication date: August 10, 2017Inventors: Edmund Blackshear, Keiichi Hirabayashi, Yoichi Miyazawa, Brian W. Quinlan, Junji Sato
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Patent number: 9659131Abstract: An approach is provided in which a laminate substrate includes top layers, bottom layers, and a core layer. The top layers are positioned between the core layer and a top surface metallurgy (TSM) layer and include at least one top conductive layer. The bottom layers are positioned between the core layer and a bottom surface metallurgy (BSM) layer and include at least one bottom conductive layer includes a material void pattern that is based upon the top conductive layer and reduces warpage of the laminate substrate.Type: GrantFiled: June 29, 2015Date of Patent: May 23, 2017Assignee: GLOBALFOUNDRIES INC.Inventors: Edmund Blackshear, Anson Jay Call, Vijayeshwar Das Khanna, Douglas Oliver Powell, David John Russell
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Patent number: 9543253Abstract: A method including providing a laminate substrate, characterizing the laminate substrate for warpage characteristics, determining a horizontal plane distortion based on the warpage characteristics, and placing the laminate substrate into a fixture with an adjustment to correct the horizontal plane distortion, the adjustment being located in a center of the laminate substrate, wherein the adjustment contacts the laminate substrate. The method may further include fluxing the laminate substrate, placing a chip onto the laminate substrate, and placing the fixture into a reflow furnace to join the chip and the laminate substrate.Type: GrantFiled: January 16, 2015Date of Patent: January 10, 2017Assignee: GLOBALFOUNDRIES INC.Inventors: Edmund Blackshear, Thomas E. Lombardi, Donald A. Merte, Steven P. Ostrander, Thomas Weiss, Jiantao Zheng
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Publication number: 20160211161Abstract: A clamping apparatus applies a force to a workpiece during processing. The clamping apparatus includes a base defining a work area configured to receive a joined structure having multiple elements. The base defines a recess in the work area. An adjustable mechanism is configured to releasably couple to the base and apply a adjustable downward force to the joined structure to bend the joined structure downwardly into the recess during a process. A resilient plunger is part of the adjustable mechanism. The resilient plunger extends downwardly from a top plate of the adjustable mechanism, and the resilient plunger is configured to contact a top of a first element of the joined structure to apply the downward force.Type: ApplicationFiled: March 30, 2016Publication date: July 21, 2016Inventors: Edmund Blackshear, Vijayeshwar D. Khanna, Oswald J. Mantilla
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Publication number: 20160163611Abstract: A laminate substrate for receiving a semiconductor chip. Included are laminate layers stacked to form the laminate substrate, each laminate layer includes a core that includes particle-filled epoxy and a metallic layer on the core. At least one laminate layer has a radial cut through the metallic layer, the radial cut extending from a periphery of the at least one laminate layer towards a center of the at least one laminate layer. The radial cut cuts only through the metallic layer and does not cut through the core.Type: ApplicationFiled: December 3, 2014Publication date: June 9, 2016Inventors: Edmund Blackshear, Shidong Li
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Patent number: 9305894Abstract: A clamping apparatus applies a force to a workpiece during processing. The clamping apparatus includes a base defining a work area configured to receive a joined structure having multiple elements. The base defines a recess in the work area. An adjustable mechanism is configured to releasably couple to the base and apply a adjustable downward force to the joined structure to bend the joined structure downwardly into the recess during a process. A resilient plunger is part of the adjustable mechanism. The resilient plunger extends downwardly from a top plate of the adjustable mechanism, and the resilient plunger is configured to contact a top of a first element of the joined structure to apply the downward force.Type: GrantFiled: June 5, 2013Date of Patent: April 5, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Edmund Blackshear, Vijayeshwar D. Khanna, Oswald J. Mantilla
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Patent number: 9293439Abstract: An improved electronic module assembly and method of fabrication is disclosed. A patterned array of adhesive is deposited on a laminate, to which a chip is attached. Each region of adhesive is referred to as a lid tie. A lid is placed on the laminate, and is in contact with the lid ties. The lid ties serve to add stability to the laminate and reduce flexing during thermal processing and mechanical stress.Type: GrantFiled: December 11, 2014Date of Patent: March 22, 2016Assignee: GLOBALFOUNDRIES Inc.Inventors: Edmund Blackshear, Elaine Cyr, Benjamin Vito Fasano, Paul Francis Fortier, Marcus E. Interrante, Roger Lam, Shidong Li, Thomas Edward Lombardi, Hilton T. Toy, Thomas Weiss
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Publication number: 20150317423Abstract: An approach is provided in which a laminate substrate includes top layers, bottom layers, and a core layer. The top layers are positioned between the core layer and a top surface metallurgy (TSM) layer and include at least one top conductive layer. The bottom layers are positioned between the core layer and a bottom surface metallurgy (BSM) layer and include at least one bottom conductive layer includes a material void pattern that is based upon the top conductive layer and reduces warpage of the laminate substrate.Type: ApplicationFiled: June 29, 2015Publication date: November 5, 2015Inventors: Edmund Blackshear, Anson Jay Call, Vijayeshwar Das Khanna, Douglas Oliver Powell, David John Russell
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Patent number: 9105535Abstract: An approach is provided in which a laminate substrate includes top layers, bottom layers, and a core layer. The top layers are positioned between the core layer and a top surface metallurgy (TSM) layer and include at least one top conductive layer. The bottom layers are positioned between the core layer and a bottom surface metallurgy (BSM) layer and include at least one bottom conductive layer that includes a material void pattern that is based upon the top conductive layer and reduces warpage of the laminate substrate.Type: GrantFiled: June 19, 2012Date of Patent: August 11, 2015Assignee: International Business Machines CorporationInventors: Edmund Blackshear, Anson Jay Call, Vijayeshwar Das Khanna, Douglas Oliver Powell, David John Russell
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Patent number: 9093563Abstract: An improved electronic module assembly and method of fabrication is disclosed. A patterned array of adhesive is deposited on a laminate, to which a chip is attached. Each region of adhesive is referred to as a lid tie. A lid is placed on the laminate, and is in contact with the lid ties. The lid ties serve to add stability to the laminate and reduce flexing during thermal processing and mechanical stress.Type: GrantFiled: July 11, 2013Date of Patent: July 28, 2015Assignee: International Business Machines CorporationInventors: Edmund Blackshear, Elaine Cyr, Benjamin Vito Fasano, Paul Francis Fortier, Marcus E. Interrante, Roger Lam, Shidong Li, Thomas Edward Lombardi, Hilton T. Toy, Thomas Weiss
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Patent number: 9048245Abstract: A method including providing a fixture comprising a trap ring, a base plate having a recess adapted to receive a laminate substrate, the base plate including an opening and an adjustable height center button disposed in the opening, the opening being located within the recess and located in a center of the laminate substrate, characterizing the laminate substrate for warpage characteristics by using one of room temperature techniques and elevated temperature techniques, determining a horizontal plane distortion based on the warpage characteristics, and placing the laminate substrate into the fixture with an adjustment to correct the horizontal plane distortion, the adjustment is provided by the adjustable height center button, wherein the adjustable height center button contacts the laminate substrate. The method further includes fluxing the laminate substrate, placing a chip onto the laminate substrate, and placing the fixture into a reflow furnace to join the chip and the laminate substrate.Type: GrantFiled: June 5, 2012Date of Patent: June 2, 2015Assignee: International Business Machines CorporationInventors: Edmund Blackshear, Thomas E. Lombardi, Donald A. Merte, Steven P. Ostrander, Thomas Weiss, Jiantao Zheng
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Patent number: 9040388Abstract: A patterned adhesive layer including holes is employed to attach a coreless substrate layer to a stiffener. The patterned adhesive layer is confined to kerf regions, which are subsequently removed during singulation. Each hole in the patterned adhesive layer has an area that is greater than the area of a bottomside interconnect footprint of the coreless substrate. The patterned adhesive layer may include a permanent adhesive that is thermally curable or ultraviolet-curable. The composition of the stiffener can be tailored so that the thermal coefficient of expansion of the stiffener provides tensile stress to the coreless substrate layer at room temperature and at the bonding temperature. The tensile stress applied to the coreless substrate layer prevents or reduces warpage of the coreless substrate layer during bonding. Upon dicing, bonded stacks of a semiconductor chip and a coreless substrate can be provided without adhesive thereupon.Type: GrantFiled: February 15, 2013Date of Patent: May 26, 2015Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventor: Edmund Blackshear
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Publication number: 20150136838Abstract: A method including providing a laminate substrate, characterizing the laminate substrate for warpage characteristics, determining a horizontal plane distortion based on the warpage characteristics, and placing the laminate substrate into a fixture with an adjustment to correct the horizontal plane distortion, the adjustment being located in a center of the laminate substrate, wherein the adjustment contacts the laminate substrate. The method may further include fluxing the laminate substrate, placing a chip onto the laminate substrate, and placing the fixture into a reflow furnace to join the chip and the laminate substrate.Type: ApplicationFiled: January 16, 2015Publication date: May 21, 2015Inventors: Edmund Blackshear, Thomas E. Lombardi, Donald A. Merte, Steven P. Ostrander, Thomas Weiss, Jiantao Zheng
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Publication number: 20150093859Abstract: An improved electronic module assembly and method of fabrication is disclosed. A patterned array of adhesive is deposited on a laminate, to which a chip is attached. Each region of adhesive is referred to as a lid tie. A lid is placed on the laminate, and is in contact with the lid ties. The lid ties serve to add stability to the laminate and reduce flexing during thermal processing and mechanical stress.Type: ApplicationFiled: December 11, 2014Publication date: April 2, 2015Applicant: International Business Machines CorporationInventors: Edmund Blackshear, Elaine Cyr, Benjamin Vito Fasano, Paul Francis Fortier, Marcus E. Interrante, Roger Lam, Shidong Li, Thomas Edward Lombardi, Hilton T. Toy, Thomas Weiss