Abstract: A multi-layer substrate with metal layers as a moisture diffusion barrier for reduced electrical performance degradation over time after moisture exposure and methods of design and manufacture. The method includes determining a diffusion rate of an insulator material provided between an upper metal layer and an underlying signal line. The method further includes calculating a diffusion distance between a plane opening of the upper metal layer and the underlying signal line using the diffusion rate of the insulator material.

Abstract: A multi-layer substrate with metal layers as a moisture diffusion barrier for reduced electrical performance degradation over time after moisture exposure and methods of design and manufacture. The method includes determining a diffusion rate of an insulator material provided between an upper metal layer and an underlying signal line. The method further includes calculating a diffusion distance between a plane opening of the upper metal layer and the underlying signal line using the diffusion rate of the insulator material.

Abstract: A multi-layer substrate with metal layers as a moisture diffusion barrier for reduced electrical performance degradation over time after moisture exposure and methods of design and manufacture. The method includes determining a diffusion rate of an insulator material provided between an upper metal layer and an underlying signal line. The method further includes calculating a diffusion distance between a plane opening of the upper metal layer and the underlying signal line using the diffusion rate of the insulator material.

Abstract: A photonic integrated circuit (PIC) fan-out package and related methods of forming same are disclosed. The PIC fan-out package includes: an overmold body; a PIC die in the overmold body, the PIC die including electro-optic circuitry; a plurality of optical fiber stubs operatively coupled to the electro-optic circuitry; an edge fiber coupling interface in a lateral side of the overmold body for coupling the plurality of optical fiber stubs to external optical fibers using a connector; an ancillary device in the overmold body; a redistribution wiring layer (RDL) interposer adjacent the overmold body and electrically connected to the PIC die and the ancillary device; and a ball grid array (BGA) electrically coupled to the PIC die and the ancillary device by the RDL interposer, the BGA configured to electrically couple the PIC die and the ancillary device to a printed circuit board (PCB).

Abstract: A photonic integrated circuit (PIC) fan-out package and related methods of forming same are disclosed. The PIC fan-out package includes: an overmold body; a PIC die in the overmold body, the PIC die including electro-optic circuitry; a plurality of optical fiber stubs operatively coupled to the electro-optic circuitry; an edge fiber coupling interface in a lateral side of the overmold body for coupling the plurality of optical fiber stubs to external optical fibers using a connector; an ancillary device in the overmold body; a redistribution wiring layer (RDL) interposer adjacent the overmold body and electrically connected to the PIC die and the ancillary device; and a ball grid array (BGA) electrically coupled to the PIC die and the ancillary device by the RDL interposer, the BGA configured to electrically couple the PIC die and the ancillary device to a printed circuit board (PCB).

Abstract: A multi-layer substrate with metal layers as a moisture diffusion barrier for reduced electrical performance degradation over time after moisture exposure and methods of design and manufacture. The method includes determining a diffusion rate of an insulator material provided between an upper metal layer and an underlying signal line. The method further includes calculating a diffusion distance between a plane opening of the upper metal layer and the underlying signal line using the diffusion rate of the insulator material.

Abstract: A multi-layer substrate with metal layers as a moisture diffusion barrier for reduced electrical performance degradation over time after moisture exposure and methods of design and manufacture. The method includes determining a diffusion rate of an insulator material provided between an upper metal layer and an underlying signal line. The method further includes calculating a diffusion distance between a plane opening of the upper metal layer and the underlying signal line using the diffusion rate of the insulator material.

Abstract: A multi-layer substrate with metal layers as a moisture diffusion barrier for reduced electrical performance degradation over time after moisture exposure and methods of design and manufacture. The method includes determining a diffusion rate of an insulator material provided between an upper metal layer and an underlying signal line. The method further includes calculating a diffusion distance between a plane opening of the upper metal layer and the underlying signal line using the diffusion rate of the insulator material.

Abstract: A method for shaping a laminate substrate includes characterizing the laminate substrate for warpage characteristics over a range of temperatures. The laminate substrate is placed into a shaping fixture with any necessary correction to obtain a flat laminate substrate chip site area at a chip join temperature. The laminate substrate is shaped at a temperature greater than or equal to a maximum laminate substrate fabrication temperature. The shape of the laminate substrate is retained when it is removed from the shaping fixture.

Abstract: A fixture for shaping a laminate substrate includes a trap ring, a base plate and a center button. The base plate includes a recess adapted to receive the laminate substrate. The center button is disposed in an opening in the base plate. The center button may be adjusted to shape the laminate substrate.

Abstract: A method for shaping a laminate substrate includes characterizing the laminate substrate for warpage characteristics over a range of temperatures. The laminate substrate is placed into a shaping fixture with any necessary correction to obtain a flat laminate substrate chip site area at a chip join temperature. The laminate substrate is shaped at a temperature greater than or equal to a maximum laminate substrate fabrication temperature. The shape of the laminate substrate is retained when it is removed from the shaping fixture.

Abstract: A fixture for shaping a laminate substrate includes a trap ring, a base plate and a center button. The base plate includes a recess adapted to receive the laminate substrate. The center button is disposed in an opening in the base plate. The center button may be adjusted to shape the laminate substrate.

Abstract: Embodiments of the present invention provide a system and method for manufacturing integrated circuit (IC) chip packages. In one embodiment, the integrated circuit (IC) chip package can include an IC chip and a substrate coupled to the IC chip. The substrate can include a glass fiber re-enforced epoxy core, a plurality copper circuitry containing particle re-enforced epoxy layers symmetrically-oriented to each surface of the glass fiber re-enforced epoxy core, and an outermost amorphous glass layer on each surface of the plurality of layers. The IC chip can be coupled to copper circuitry bonded to one of the outermost amorphous glass layers.

Abstract: A structure comprises: a substrate; at least one conductor on the substrate; at least one contact pad on the substrate; a mask over the conductor (wherein the mask comprises an opening over the contact pad and wherein the mask comprises a bottom surface contacting the substrate and a top surface opposite the bottom surface); and a contact pad plating layer on the contact pad and within the opening of the mask. The contact pad plating layer comprises a bottom surface contacting the contact pad and a top surface opposite the bottom surface, and the top surface of the contact pad plating layer is coplanar with the top surface of the mask.

Abstract: An approach to DRAM memory chip packaging leveraging the chip center position for wire bond pads to minimize time-of-flight and impedance effects resulting from stacking in a BGA application. A top layer of a dual device stack of center bus chips is stacked with an offset in a single direction with respect to a bottom layer of the dual device stack. The top layer of chips may be wire bonded to the opposite side of the module substrate. The center bus may be made to traverse to the substrate between two memory devices on the lower layer. To assemble the offset stacking devices into a high density module, devices are placed sequentially on a module substrate such that approximately one half of the protruding lower memory device is used as a support for the overhanging upper memory device chip of the next device stack.

Abstract: A method and structure for a memory structure that includes a plurality of substrates stacked one on another is disclosed. The invention includes a plurality of connectors connecting the substrates to one another and a plurality of memory chip packages mounted on the substrates. The connectors have a size sufficient to form a gap between the substrates. The gap is larger than a height of the memory chip packages.

Abstract: A method and structure for a memory structure that includes a plurality of substrates stacked one on another is disclosed. The invention includes a plurality of connectors connecting the substrates to one another and a plurality of memory chip packages mounted on the substrates. The connectors have a size sufficient to form a gap between the substrates. The gap is larger than a height of the memory chip packages.

Abstract: An integrated circuit chip package wherein the chip is encapsulated prior to mechanical bonding to a packaging substrate. The package provides a continuous adhesive interface between the encapsulated chip and surrounding encapsulant, and the substrate. This structure eliminates discontinuities in flatness and their associated stress states resulting in more reliable package contacts.

Abstract: A three-dimensional memory module in a repetitively used pedestal connector provides signal paths unique and common to the module at its level and signal paths from the level below unique to and common to modules at levels above. In order to provide a unique signal path from a substrate to each memory module, while using identical pedestal connectors at each level, signal lines are skewed from where they enter the bottom surface of the pedestal connector to where they exit the top surface. For example, each input in a line of inputs is connected to a matching line of outputs, but with a shift of one position between input and output.

Abstract: A three-dimensional memory module in a repetitively used pedestal connector provides signal paths unique and common to the module at its level and signal paths from the level below unique to and common to modules at levels above. In order to provide a unique signal path from a substrate to each memory module, while using identical pedestal connectors at each level, signal lines are skewed from where they enter the bottom surface of the pedestal connector to where they exit the top surface. For example, each input in a line of inputs is connected to a matching line of outputs, but with a shift of one position between input and output.