Patents by Inventor Edmund J. Kelly

Edmund J. Kelly has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210197949
    Abstract: The present invention is realized by apparatus and methods for harvesting, storing, and generating energy by permanently placing a large rigid buoyant platform high in the earth's atmosphere, above clouds, moisture, dust, and wind. Long, strong and light tethers can connect the buoyant structure to the ground which can hold it in position against wind forces. Weights suspended from the buoyant platform with cables are raised and lowered by electric winches to store and release gravitational potential energy. High voltage transmission lines electrically connect the platform to the earth's surface. Electrical energy from the high voltage transmission lines or from photovoltaic arrays on the platform can be stored as gravitational potential energy and subsequently released as electricity from generators driven from the stored gravitational potential energy and used on the platform or transmitted via the high voltage transmission lines.
    Type: Application
    Filed: January 29, 2020
    Publication date: July 1, 2021
    Applicant: STRATOSOLAR, INC.
    Inventors: EDMUND J. KELLY, ROGER ARNOLD
  • Publication number: 20210197948
    Abstract: The present invention is realized by apparatus and methods for harvesting, storing, and generating energy by permanently placing a large rigid buoyant platform high in the earth's atmosphere, above clouds, moisture, dust, and wind. Long, strong and light tethers can connect the buoyant structure to the ground which can hold it in position against wind forces. Weights suspended from the buoyant platform with cables are raised and lowered by electric winches to store and release gravitational potential energy. High voltage transmission lines electrically connect the platform to the earth's surface. Electrical energy from the high voltage transmission lines or from photovoltaic arrays on the platform can be stored as gravitational potential energy and subsequently released as electricity from generators driven from the stored gravitational potential energy and used on the platform or transmitted via the high voltage transmission lines.
    Type: Application
    Filed: January 29, 2020
    Publication date: July 1, 2021
    Applicant: STRATOSOLAR, INC.
    Inventors: EDMUND J. KELLY, ROGER ARNOLD
  • Publication number: 20210197950
    Abstract: The present invention is realized by apparatus and methods for harvesting, storing, and generating energy by permanently placing a large rigid buoyant platform high in the earth's atmosphere, above clouds, moisture, dust, and wind. Long, strong and light tethers can connect the buoyant structure to the ground which can hold it in position against wind forces. Weights suspended from the buoyant platform with cables are raised and lowered by electric winches to store and release gravitational potential energy. High voltage transmission lines electrically connect the platform to the earth's surface. Electrical energy from the high voltage transmission lines or from photovoltaic arrays on the platform can be stored as gravitational potential energy and subsequently released as electricity from generators driven from the stored gravitational potential energy and used on the platform or transmitted via the high voltage transmission lines.
    Type: Application
    Filed: January 29, 2020
    Publication date: July 1, 2021
    Applicant: STRATOSOLAR, INC.
    Inventors: EDMUND J. KELLY, ROGER ARNOLD
  • Patent number: 8825897
    Abstract: A cluster of computers including a plurality of processing nodes, a command network connecting to each of the processor nodes, and circuitry for addressing each of the processor nodes on the command network based on a position of the processor node on the command network.
    Type: Grant
    Filed: September 24, 2004
    Date of Patent: September 2, 2014
    Assignee: Oracle America, Inc.
    Inventor: Edmund J. Kelly
  • Patent number: 8719544
    Abstract: A method of responding to an attempt to write a memory address including a target instruction which has been translated to a host instruction for execution by a host processor including the steps of marking a memory address including a target instruction which has been translated to a host instruction, detecting a memory address which has been marked when an attempt is made to write to the memory address, and responding to the detection of a memory address which has been marked by protecting a target instruction at the memory address until it has been assured that translations associated with the memory address will not be utilized before being updated.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: May 6, 2014
    Inventors: Edmund J. Kelly, Robert F. Cmelik, Malcolm J. Wing
  • Publication number: 20120110306
    Abstract: A method of responding to an attempt to write a memory address including a target instruction which has been translated to a host instruction for execution by a host processor including the steps of marking a memory address including a target instruction which has been translated to a host instruction, detecting a memory address which has been marked when an attempt is made to write to the memory address, and responding to the detection of a memory address which has been marked by protecting a target instruction at the memory address until it has been assured that translations associated with the memory address will not be utilized before being updated.
    Type: Application
    Filed: September 23, 2011
    Publication date: May 3, 2012
    Inventors: Edmund J. Kelly, Robert F. Cmelik, Malcolm J. Wing
  • Patent number: 8055877
    Abstract: A method of responding to an attempt to write a memory address including a target instruction which has been translated to a host instruction for execution by a host processor including the steps of marking a memory address including a target instruction which has been translated to a host instruction, detecting a memory address which has been marked when an attempt is made to write to the memory address, and responding to the detection of a memory address which has been marked by protecting a target instruction at the memory address until it has been assured that translations associated with the memory address will not be utilized before being updated.
    Type: Grant
    Filed: October 11, 2005
    Date of Patent: November 8, 2011
    Inventors: Edmund J. Kelly, Robert F. Cmelik, Malcolm J. Wing
  • Patent number: 7840776
    Abstract: A method of responding to an attempt to write a memory address including a target instruction which has been translated to a host instruction for execution by a host processor including the steps of marking a memory address including a target instruction which has been translated to a host instruction, detecting a memory address which has been marked when an attempt is made to write to the memory address, and responding to the detection of a memory address which has been marked by protecting a target instruction at the memory address until it has been assured that translations associated with the memory address will not be utilized before being updated.
    Type: Grant
    Filed: October 30, 2000
    Date of Patent: November 23, 2010
    Inventors: Edmund J. Kelly, Robert F. Cmelik, Malcolm J. Wing
  • Publication number: 20100205413
    Abstract: A method of responding to an attempt to write a memory address including a target instruction which has been translated to a host instruction for execution by a host processor including the steps of marking a memory address including a target instruction which has been translated to a host instruction, detecting a memory address which has been marked when an attempt is made to write to the memory address, and responding to the detection of a memory address which has been marked by protecting a target instruction at the memory address until it has been assured that translations associated with the memory address will not be utilized before being updated.
    Type: Application
    Filed: April 16, 2010
    Publication date: August 12, 2010
    Inventors: Edmund J. Kelly, Robert F. Cmelik, Malcolm J. Wing
  • Patent number: 7716452
    Abstract: A method of responding to an attempt to write a memory address including a target instruction which has been translated to a host instruction for execution by a host processor including the steps of marking a memory address including a target instruction which has been translated to a host instruction, detecting a memory address which has been marked when an attempt is made to write to the memory address, and responding to the detection of a memory address which has been marked by protecting a target instruction at the memory address until it has been assured that translations associated with the memory address will not be utilized before being updated.
    Type: Grant
    Filed: May 13, 2003
    Date of Patent: May 11, 2010
    Inventors: Edmund J. Kelly, Robert F. Cmelik, Malcolm J. Wing
  • Patent number: 7366889
    Abstract: Apparatus and a method for booting each of a plurality of computer processor nodes in a cluster system to run the same cluster operating system.
    Type: Grant
    Filed: August 27, 2004
    Date of Patent: April 29, 2008
    Assignee: Sun Microsystems, Inc.
    Inventor: Edmund J. Kelly
  • Patent number: 6199152
    Abstract: A method of responding to an attempt to write a memory address including a target instruction which has been translated to a host instruction for execution by a host processor including the steps of marking a memory address including a target instruction which has been translated to a host instruction, detecting a memory address which has been marked when an attempt is made to write to the memory address, and responding to the detection of a memory address which has been marked by protecting a target instruction at the memory address until it has been assured that translations associated with the memory address will not be utilized before being updated.
    Type: Grant
    Filed: August 22, 1996
    Date of Patent: March 6, 2001
    Assignee: Transmeta Corporation
    Inventors: Edmund J. Kelly, Robert F. Cmelik, Malcolm J. Wing
  • Patent number: 6031992
    Abstract: A microprocessor for a host computer designed to execute target application programs for a target computer having a target instruction set including the combination of code morphing software, and morph host processing hardware designed to execute instructions of a host instruction set, the combination of the code morphing software and the morph host processing hardware comprising means to translate a set of target instructions into instructions of a host instruction set, means to optimize the instructions of the host instruction set translated from the target application program speculating upon the occurrence of a condition, means to determine under control of the code morphing software official state of the target computer which existed at the beginning of a translation of a set of target instructions during execution of the target application program by the microprocessor, means for updating state of the target computer from state of the host computer when a set of host instructions executes in accordance
    Type: Grant
    Filed: July 5, 1996
    Date of Patent: February 29, 2000
    Assignee: Transmeta Corporation
    Inventors: Robert F. Cmelik, David R. Ditzel, Edmund J. Kelly, Colin B. Hunter, Douglas A. Laird, Malcolm John Wing, Grzegorz B. Zyner
  • Patent number: 5958061
    Abstract: Apparatus for use in a processing system having a host processor capable of executing a first instruction set to assist in running instructions of a different instruction set which is translated to the first instruction set by the host processor including circuitry for temporarily storing memory stores generated until a determination that a sequence of translated instructions will execute without exception or error on the host processor, circuitry for permanently storing memory stores temporarily stored when a determination is made that a sequence of translated instructions will execute without exception or error on the host processor, and circuitry for eliminating memory stores temporarily stored when a determination is made that a sequence of translated instructions will generate an exception or error on the host processor.
    Type: Grant
    Filed: July 24, 1996
    Date of Patent: September 28, 1999
    Assignee: Transmeta Corporation
    Inventors: Edmund J. Kelly, Malcolm John Wing
  • Patent number: 5926832
    Abstract: Apparatus and a method for storing data already stored at an often utilized memory address in registers local to a host processor and maintain the data in the registers and memory consistent so that the processor may respond more rapidly when a memory address is to be accessed.
    Type: Grant
    Filed: September 26, 1996
    Date of Patent: July 20, 1999
    Assignee: Transmeta Corporation
    Inventors: Malcolm J. Wing, Edmund J. Kelly
  • Patent number: 5832205
    Abstract: A memory controller for a microprocessor including apparatus to both detect a failure of speculation on the nature of the memory being addressed, and apparatus to recover from such failures.
    Type: Grant
    Filed: August 20, 1996
    Date of Patent: November 3, 1998
    Assignee: Transmeta Corporation
    Inventors: Edmund J. Kelly, Robert F. Cmelik, Malcolm John Wing
  • Patent number: 4803621
    Abstract: A memory architecture having particular application for use in computer systems employing virtual memory techniques. A processor provides row and column addresses to access data stored in a dynamic random access memory (DRAM). The virtual address supplied by the processor includes high and low order bits. In the present embodiment, the high order bits represent a virtual row address and the low order bits represent a real column address. The virtual row address is applied to a memory management unit (MMU) for translation into a real row address. The real column address need not be translated. A comparator compares the current virtual row address to the previous row address stored in a latch. If the current row and previous row addresses match, a cycle control circuit couples the real column address to the DRAM, and applies a strobe signal such that the desired data is accessed in the memory without the need to reapply the row address.
    Type: Grant
    Filed: July 24, 1986
    Date of Patent: February 7, 1989
    Assignee: Sun Microsystems, Inc.
    Inventor: Edmund J. Kelly