Patents by Inventor Edward Joseph Nowak

Edward Joseph Nowak has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10290549
    Abstract: The disclosure is directed to gate all-around integrated circuit structures, finFETs having a dielectric isolation, and methods of forming the same. The gate all-around integrated circuit structure may include a first insulator region within a substrate; a pair of remnant liner stubs disposed within the first insulator region; a second insulator region laterally adjacent to the first insulator region within the substrate; a pair of fins over the first insulator region, each fin in the pair of fins including an inner sidewall facing the inner sidewall of an adjacent fin in the pair of fins and an outer sidewall opposite the inner sidewall; and a gate structure substantially surrounding an axial portion of the pair of fins and at least partially disposed over the first and second insulator regions, wherein each remnant liner stub is substantially aligned with the inner sidewall of a respective fin of the pair of fins.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: May 14, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ruilong Xie, Julien Frougier, Min Gyu Sung, Edward Joseph Nowak, Nigel G. Cave, Lars Liebmann, Daniel Chanemougame, Andreas Knorr
  • Publication number: 20190074224
    Abstract: The disclosure is directed to gate all-around integrated circuit structures, finFETs having a dielectric isolation, and methods of forming the same. The gate all-around integrated circuit structure may include a first insulator region within a substrate; a pair of remnant liner stubs disposed within the first insulator region; a second insulator region laterally adjacent to the first insulator region within the substrate; a pair of fins over the first insulator region, each fin in the pair of fins including an inner sidewall facing the inner sidewall of an adjacent fin in the pair of fins and an outer sidewall opposite the inner sidewall; and a gate structure substantially surrounding an axial portion of the pair of fins and at least partially disposed over the first and second insulator regions, wherein each remnant liner stub is substantially aligned with the inner sidewall of a respective fin of the pair of fins.
    Type: Application
    Filed: September 5, 2017
    Publication date: March 7, 2019
    Inventors: Ruilong Xie, Julien Frougier, Min Gyu Sung, Edward Joseph Nowak, Nigel G. Cave, Lars Liebmann, Daniel Chanemougame, Andreas Knorr
  • Patent number: 8963294
    Abstract: A method, structure and alignment procedure, for forming a finFET. The method including, defining a first fin of the finFET with a first mask and defining a second fin of the finFET with a second mask. The structure including integral first and second fins of single-crystal semiconductor material and longitudinal axes of the first and second fins aligned in the same crystal direction but offset from each other. The alignment procedure including simultaneously aligning alignment marks on a gate mask to alignment targets formed separately by a first masked used to define the first fin and a second mask used to define the second fin.
    Type: Grant
    Filed: September 19, 2007
    Date of Patent: February 24, 2015
    Assignee: International Business Machines Corporation
    Inventors: Jochen Beintner, Thomas Ludwig, Edward Joseph Nowak
  • Patent number: 8586488
    Abstract: A computer program product and system for configuring J electromagnetic radiation sources (J?2) to simultaneously irradiate a substrate. Each source has a different function of wavelength and angular distribution of emitted radiation. The substrate includes a base layer and I stacks (I?2) thereon. Pj denotes a same source-specific normally incident energy flux on each stack from source j. For simultaneous exposure of the I stacks to radiation from the J sources, Pj is computed such that an error E being a function of |W1?S1|, |W2?S2|, |WI?SI| is about minimized with respect to Pj (j=1, . . . , J). Wi and Si respectively denote an actual and target energy flux transmitted into the substrate via stack i (i=1, . . . , I). The stacks are exposed to the radiation from the sources characterized by the computed Pj (j=1, . . . , J).
    Type: Grant
    Filed: August 23, 2010
    Date of Patent: November 19, 2013
    Assignee: International Business Machines Corporation
    Inventors: Brent Alan Anderson, Edward Joseph Nowak
  • Patent number: 8518757
    Abstract: A strained semiconductor structure and method of making the structure. The method includes: forming a pad layer on a top surface of a silicon layer of a substrate, the substrate comprising the silicon layer separated from a supporting substrate by a buried oxide layer; forming openings in the pad layer and etching trenches through the silicon layer to the buried oxide layer in the openings to form silicon regions from the silicon layer; forming spacers on the entirety of sidewalls of the silicon regions exposed in the trenches; forming oxide regions in corners of the silicon regions proximate to both the sidewalls and the buried oxide layer to form strained silicon regions, the oxide regions not extending to the pad layer; and removing at least a portion of the spacers and filling remaining spaces in the trenches with silicon to form filled regions abutting the strained silicon region.
    Type: Grant
    Filed: February 18, 2010
    Date of Patent: August 27, 2013
    Assignee: International Business Machines Corporation
    Inventors: Brent Alan Anderson, Edward Joseph Nowak
  • Patent number: 8466503
    Abstract: A semiconductor transistor with an expanded top portion of a gate and a method for forming the same. The semiconductor transistor with an expanded top portion of a gate includes (a) a semiconductor region which includes a channel region and first and second source/drain regions; the channel region is disposed between the first and second source/drain regions, (b) a gate dielectric region in direct physical contact with the channel region, and (c) a gate electrode region which includes a top portion and a bottom portion. The bottom portion is in direct physical contact with the gate dielectric region. A first width of the top portion is greater than a second width of the bottom portion. The gate electrode region is electrically insulated from the channel region by the gate dielectric region.
    Type: Grant
    Filed: August 11, 2008
    Date of Patent: June 18, 2013
    Assignee: International Business Machines Corporation
    Inventors: Brent Alan Anderson, Victor W. C. Chan, Edward Joseph Nowak
  • Patent number: 8354351
    Abstract: A system for configuring and utilizing J electromagnetic radiation sources (J?2) to serially irradiate a substrate. Each source has a different function of wavelength and angular distribution of emitted radiation. The substrate includes a base layer and I stacks (I?2; J?I) thereon. Pj denotes a same source-specific normally incident energy flux on each stack from source j. In each of I independent exposure steps, the I stacks are concurrently exposed to radiation from the J sources. Vi and Si respectively denote an actual and target energy flux transmitted into the substrate via stack i in exposure step i (i=1, . . . , I). t(i) and Pt(i) are computed such that: Vi is maximal through deployment of source t(i) as compared with deployment of any other source for i=1, . . . , I; and an error E being a function of |V1?S1|, |V2?S2|, . . . , |VI?SI| is about minimized with respect to Pi (i=1, . . . , I).
    Type: Grant
    Filed: November 2, 2009
    Date of Patent: January 15, 2013
    Assignee: International Business Machines Corporation
    Inventors: Brent Alan Anderson, Edward Joseph Nowak
  • Patent number: 8039376
    Abstract: A method for forming a semiconductor structure. The method includes providing a semiconductor structure including a semiconductor substrate. The semiconductor substrate includes (i) a top substrate surface which defines a reference direction perpendicular to the top substrate surface and (ii) a semiconductor body region. The method further includes implanting an adjustment dose of dopants of a first doping polarity into the semiconductor body region by an adjustment implantation process. Ion bombardment of the adjustment implantation process is in the reference direction. The method further includes (i) patterning the semiconductor substrate resulting in side walls of the semiconductor body region being exposed to a surrounding ambient and then (ii) implanting a base dose of dopants of a second doping polarity into the semiconductor body region by a base implantation process. Ion bombardment of the base implantation process is in a direction which makes a non-zero angle with the reference direction.
    Type: Grant
    Filed: November 14, 2007
    Date of Patent: October 18, 2011
    Assignee: International Business Machines Corporation
    Inventors: William F. Clark, Jr., Edward Joseph Nowak
  • Publication number: 20110198695
    Abstract: A strained semiconductor structure and method of making the structure. The method includes: forming a pad layer on a top surface of a silicon layer of a substrate, the substrate comprising the silicon layer separated from a supporting substrate by a buried oxide layer; forming openings in the pad layer and etching trenches through the silicon layer to the buried oxide layer in the openings to form silicon regions from the silicon layer; forming spacers on the entirety of sidewalls of the silicon regions exposed in the trenches; forming oxide regions in corners of the silicon regions proximate to both the sidewalls and the buried oxide layer to form strained silicon regions, the oxide regions not extending to the pad layer; and removing at least a portion of the spacers and filling remaining spaces in the trenches with silicon to form filled regions abutting the strained silicon region.
    Type: Application
    Filed: February 18, 2010
    Publication date: August 18, 2011
    Applicant: International Business Machines Corporation
    Inventors: Brent Alan Anderson, Edward Joseph Nowak
  • Patent number: 7982269
    Abstract: A semiconductor structure. The structure includes (a) a fin region having (i) a first source/drain portion having a first surface and a third surface, wherein the first and third surfaces are (A) parallel to each other and (B) not coplanar, (ii) a second source/drain portion having a second surface and a fourth surface, wherein the second and fourth surfaces are (A) parallel to each other and (B) not coplanar, and (iii) a channel region; (b) a gate dielectric layer; (c) a gate electrode region, wherein the gate dielectric layer (i) is sandwiched between, and (ii) electrically insulates the gate electrode region and the channel region; and (d) first second strain creating regions on the third and fourth surfaces, respectively, wherein the first and second strain creating regions comprise a strain creating material.
    Type: Grant
    Filed: April 17, 2008
    Date of Patent: July 19, 2011
    Assignee: International Business Machines Corporation
    Inventors: Brent Alan Anderson, Andres Bryant, Edward Joseph Nowak
  • Patent number: 7964465
    Abstract: A structure formation method. First, a structure is provided including (a) a fin region comprising (i) a first source/drain portion having a first surface and a third surface parallel to each other, not coplanar, and both exposed to a surrounding ambient, (ii) a second source/drain portion having a second surface and a fourth surface parallel to each other, not coplanar, and both exposed to the surrounding ambient, and (iii) a channel region disposed between the first and second source/drain portions, (b) a gate dielectric layer, and (c) a gate electrode region, wherein the gate dielectric layer (i) is sandwiched between, and (ii) electrically insulates the gate electrode region and the channel region. Next, a patterned covering layer is used to cover the first and second surfaces but not the third and fourth surfaces. Then, the first and second source/drain portions are etched at the third and fourth surfaces, respectively.
    Type: Grant
    Filed: April 17, 2008
    Date of Patent: June 21, 2011
    Assignee: International Business Machines Corporation
    Inventors: Brent Alan Anderson, Andres Bryant, Edward Joseph Nowak
  • Patent number: 7877712
    Abstract: A verification system disclosed herein uses the unique signatures of an IC to perform authentication of the IC after the IC is shipped to a customer. The verification system records the fingerprint and associated IC identifier with the fingerprint into a data structure. The data structure is supplied to the customer for use in the customer's own security systems. When an IC interfaces with the customer's system, the verification system requests the IC's identifier and selects a data structure corresponding to that IC identifier. The verification system then performs a test on the IC (e.g. remotely operates the IC at 1V), records the resulting data and compares the test results with the corresponding data in the data structure. If a predetermined condition is satisfied then the IC is verified to be authentic. If not, the verification system responds, for example, by flagging the customer's security system.
    Type: Grant
    Filed: May 7, 2007
    Date of Patent: January 25, 2011
    Assignee: International Business Machines Corporation
    Inventors: Brent Alan Anderson, Edward Joseph Nowak
  • Publication number: 20100318210
    Abstract: A computer program product and system for configuring J electromagnetic radiation sources (J?2) to simultaneously irradiate a substrate. Each source has a different function of wavelength and angular distribution of emitted radiation. The substrate includes a base layer and I stacks (I?2) thereon. Pj denotes a same source-specific normally incident energy flux on each stack from source j. For simultaneous exposure of the I stacks to radiation from the J sources, Pj is computed such that an error E being a function of |W1?S1|, |W2?S2|, |WI?SI| is about minimized with respect to Pj (j=1, . . . , J). Wi and Si respectively denote an actual and target energy flux transmitted into the substrate via stack i (i=1, . . . , I). The stacks are exposed to the radiation from the sources characterized by the computed Pj (j=1, . . . , J).
    Type: Application
    Filed: August 23, 2010
    Publication date: December 16, 2010
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brent Alan Anderson, Edward Joseph Nowak
  • Patent number: 7851315
    Abstract: A field effect transistor and a method of fabricating the field effect transistor. The field effect transistor includes: a silicon body, a perimeter of the silicon body abutting a dielectric isolation; a source and a drain formed in the body and on opposite sides of a channel formed in the body; and a gate dielectric layer between the body and an electrically conductive gate electrode, a bottom surface of the gate dielectric layer in direct physical contact with a top surface of the body and a bottom surface the gate electrode in direct physical contact with a top surface of the gate dielectric layer, the gate electrode having a first region having a first thickness and a second region having a second thickness, the first region extending along the top surface of the gate dielectric layer over the channel region, the second thickness greater than the first thickness.
    Type: Grant
    Filed: February 26, 2008
    Date of Patent: December 14, 2010
    Assignee: International Business Machines Corporation
    Inventors: Brent Alan Anderson, Andres Bryant, William F. Clark, Jr., Edward Joseph Nowak
  • Patent number: 7821109
    Abstract: A structure and a method of making the structure. The structure includes a field effect transistor including: a first and a second source/drain formed in a silicon substrate, the first and second source/drains spaced apart and separated by a channel region in the substrate; a gate dielectric on a top surface of the substrate over the channel region; and an electrically conductive gate on a top surface of the gate dielectric; and a dielectric pillar of a first dielectric material over the gate; and a dielectric layer of a second dielectric material over the first and second source/drains, sidewalls of the dielectric pillar in direct physical contact with the dielectric layer, the dielectric pillar having no internal stress or an internal stress different from an internal stress of the dielectric layer.
    Type: Grant
    Filed: September 30, 2009
    Date of Patent: October 26, 2010
    Assignee: International Business Machines Corporation
    Inventors: Brent Alan Anderson, Edward Joseph Nowak
  • Patent number: 7790636
    Abstract: A method for configuring J electromagnetic radiation sources (J?2) to simultaneously irradiate a substrate. Each source has a different function of wavelength and angular distribution of emitted radiation. The substrate includes a base layer and I stacks (I?2) thereon. Pj denotes a same source-specific normally incident energy flux on each stack from source j. For simultaneous exposure of the I stacks to radiation from the J sources, Pj is computed such that an error E being a function of |W1?S1|, |W2?S2, . . . , |WI?SI| is about minimized with respect to Pj=1, . . . , J). Wi and Si respectively denote an actual and target energy flux transmitted into the substrate via stack i (i=1, . . . , I). The stacks are exposed to the radiation from the sources characterized by the computed Pj (j=1, . . . , J).
    Type: Grant
    Filed: June 29, 2006
    Date of Patent: September 7, 2010
    Assignee: International Business Machines Corporation
    Inventors: Brent Alan Anderson, Edward Joseph Nowak
  • Patent number: 7791166
    Abstract: A structure and a method for forming the same. The structure includes (a) a substrate which includes a top substrate surface which defines a reference direction perpendicular to the top substrate surface, (b) N semiconductor regions on the substrate, and (c) P semiconductor regions on the substrate, N and P being positive integers. The N semiconductor regions comprise dopants. The P semiconductor regions do not comprise dopants. The structure further includes M interconnect layers on top of the substrate, the N semiconductor regions, and the P semiconductor regions, M being a positive integer. The M interconnect layers include an inductor. (i) The N semiconductor regions do not overlap and (ii) the P semiconductor regions overlap the inductor in the reference direction. A plane perpendicular to the reference direction and intersecting a semiconductor region of the N semiconductor regions intersects a semiconductor region of the P semiconductor regions.
    Type: Grant
    Filed: May 4, 2007
    Date of Patent: September 7, 2010
    Assignee: International Business Machines Corporation
    Inventors: Brent Alan Anderson, Howard Smith Landis, Edward Joseph Nowak
  • Patent number: 7772656
    Abstract: A semiconductor device. The device including: a planar FET formed in a single crystal-silicon substrate, the FET comprising a first channel region, first and second source drains on opposite sides of the first channel region and a gate, the gate over the channel region and electrically isolated from the channel region by a first gate dielectric layer; and a FinFET formed in single crystal silicon block on top of and electrically isolated from the substrate, the FinFET comprising a second channel region, third and fourth source drains on opposite first and second ends of a second channel region and the gate, the gate electrically isolated from the second channel region by a second gate dielectric layer.
    Type: Grant
    Filed: December 14, 2006
    Date of Patent: August 10, 2010
    Assignee: International Business Machines Corporation
    Inventors: Brent Alan Anderson, Bryant Andres, William F. Clark, Jr., Edward Joseph Nowak
  • Patent number: 7685557
    Abstract: A mask, a method for creating a mask, and a method for irradiating a substrate through use of the mask. Creating the mask establishes the mask by designing the mask, forming the mask, or both designing and forming the mask. Creating the mask includes receiving a specified target transmittance (TS) of the substrate with respect to radiation propagated from a radiation source and transmitted through the mask with spatial selectivity in accordance with a spatially varying transmissivity (TM) of the mask with respect to the radiation. The mask is disposed between the radiation source and the substrate. The mask includes transparent portions and reflective portions distributed within the transparent portions. The first radiation after having passed through the mask is transmitted into the substrate in accordance with a spatially varying reflectance (R) of the substrate such that TM*(1?R) is about equal to TS.
    Type: Grant
    Filed: October 5, 2006
    Date of Patent: March 23, 2010
    Assignee: International Business Machines Corporation
    Inventors: Brent Alan Anderson, Edward Joseph Nowak
  • Publication number: 20100044592
    Abstract: A system for configuring and utilizing J electromagnetic radiation sources (J?2) to serially irradiate a substrate. Each source has a different function of wavelength and angular distribution of emitted radiation. The substrate includes a base layer and I stacks (I?2; J?I) thereon. Pj denotes a same source-specific normally incident energy flux on each stack from source j. In each of I independent exposure steps, the I stacks are concurrently exposed to radiation from the J sources. Vi and Si respectively denote an actual and target energy flux transmitted into the substrate via stack i in exposure step i (i=1, . . . , I). t(i) and Pt(i) are computed such that: Vi is maximal through deployment of source t(i) as compared with deployment of any other source for i=1, . . . , I; and an error E being a function of |V1?S1|, |V2?S2|, . . . , |VI?SI| is about minimized with respect to Pi (i=1, . . . , I).
    Type: Application
    Filed: November 2, 2009
    Publication date: February 25, 2010
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brent Alan Anderson, Edward Joseph Nowak