Patents by Inventor Edward L. Riegelsberger
Edward L. Riegelsberger has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9104421Abstract: A method for managing a memory controller comprising selecting a low-power state from a plurality of low-power states. The method further comprises transitioning to the low-power and entering the low-power state when the transition is complete, provided a wake-event has not been received. An apparatus comprises a controller configured to select a power state for transition, a state-machine configured to execute steps for transitions between power states of a memory controller connected by a bus to a memory, a storage configured to store at least one context, and a context engine configured to stream, at the direction of the state-machine engine, the at least one context to the memory controller. Streaming comprises communicating N portions of context data as a stream to N registers in the memory controller. A context comprises a plurality of calibrations corresponding to a state selected for transition.Type: GrantFiled: July 30, 2012Date of Patent: August 11, 2015Assignee: NVIDIA CORPORATIONInventors: Sagheer Ahmad, Edward L. Riegelsberger, Tony Yuhsiang Cheng, Laurent Rene Moll, Brian Keith Langendorf
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Patent number: 8768494Abstract: Embodiments of the invention provide a policy-based audio system. The system includes a sound application protocol interface, a configuration module and a speaker driver. The sound application protocol interface receives a set of sound samples generated by an application or event. The configuration module retrieves a first group of one or more parameters, rules and priorities applicable to the application or event. The speaker driver produces an audio output by processing the set of sound samples as a function of the group of one or more configuration parameters, rules and priorities.Type: GrantFiled: December 22, 2003Date of Patent: July 1, 2014Assignee: NVIDIA CorporationInventors: Micah S. Stroud, Stephen G. Holmes, Edward L. Riegelsberger
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Publication number: 20140032947Abstract: A method for managing a memory controller comprising selecting a low-power state from a plurality of low-power states. The method further comprises transitioning to the low-power and entering the low-power state when the transition is complete, provided a wake-event has not been received. An apparatus comprises a controller configured to select a power state for transition, a state-machine configured to execute steps for transitions between power states of a memory controller connected by a bus to a memory, a storage configured to store at least one context, and a context engine configured to stream, at the direction of the state-machine engine, the at least one context to the memory controller. Streaming comprises communicating N portions of context data as a stream to N registers in the memory controller. A context comprises a plurality of calibrations corresponding to a state selected for transition.Type: ApplicationFiled: July 30, 2012Publication date: January 30, 2014Applicant: NVIDIA CORPORATIONInventors: Sagheer Ahmad, Edward L. Riegelsberger, Tony Yuhsiang Cheng, Laurent Rene Moll, Brian Keith Langendorf
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Patent number: 8461884Abstract: According to an aspect of the present invention, one of multiple clock signals of different relative phases is selected based on a desired delay magnitude, and the digital values received on an input signal are then synchronized to an edge (“first edge”) of the selected clock signal to provide the digital values with the desired delay magnitude. In an embodiment, the selected clock signal can be delayed by a fine value (less than the minimum phase difference of the multiple clock signals) to provide a wide span of desired delays. An aspect of the invention provides for a synchronization circuit with reduced latency and which is substantially invariant to process, voltage and temperature (PVT) changes.Type: GrantFiled: August 12, 2008Date of Patent: June 11, 2013Assignee: Nvidia CorporationInventors: Jyotirmaya Swain, Utpal Barman, Adarsh Kalliat, Raji Cherian, Edward L Riegelsberger
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Patent number: 7965895Abstract: Methods, circuits, and apparatus for reducing memory bandwidth used by a graphics processor. Uncompressed tiles are read from a display buffer portion of a graphics memory and received by an encoder. The uncompressed tiles are compressed and written back to the graphics memory. When a tile is needed again before it has been modified, the compressed version is read from memory, uncompressed, and displayed. To reduce the number of unnecessary writes of compressed tiles to memory, a tile is only written to memory if it has remained static for some number of refresh cycles. Also, to prevent a large number of compressed tiles being written to the display buffer in one refresh cycle, the encoder can be throttled after a number of tiles have been written. Validity information can be stored for use by a CRTC. If a tile is updated, the validity information is updated such that invalid compressed data is not read from memory and displayed.Type: GrantFiled: August 10, 2007Date of Patent: June 21, 2011Assignee: NVIDIA CorporationInventors: John M. Danskin, Ziyad S. Hakura, Edward L. Riegelsberger, Jason M. Musicer, Stephen D. Lew
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Patent number: 7808849Abstract: Read leveling of memory units designed to receive access requests in a sequential chained topology writing a data pattern to the memory array. In an embodiment, a memory controller first writes a desired pattern into the memory array of a memory unit and then iteratively determines the accurate calibrated delay by setting a compensation delay to a test value, reading a data portion from the memory array based on the test value for the compensation delay, comparing the data portion with an expected data, determining that the test value is a calibrated compensation delay for the memory unit if the data portion equals the expected value.Type: GrantFiled: July 8, 2008Date of Patent: October 5, 2010Assignee: NVIDIA CorporationInventors: Jyotirmaya Swain, Edward L Riegelsberger, Utpal Barman
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Patent number: 7796465Abstract: A memory controller provided according to an aspect of the present invention uses a slower clock signal during write leveling compared to when performing write operations thereafter. Due to such use of a slower clock signal, the various desired delays can be determined accurately and/or easily. In an embodiment, the frequency of the slower clock signal is determined based on the maximum fly-by delay (generally the delay between sending of a signal on the shared sequential path and the receipt at the memory unit in the sequence) that may be present in the memory system. For example, if the fly by delay can be M (an integer) times the time period of the clock signal during normal write operations, the slower clock signal may have a time period of M times that of the clock signal during write operation.Type: GrantFiled: July 9, 2008Date of Patent: September 14, 2010Assignee: NVIDIA CorporationInventors: Jyotirmaya Swain, Edward L Riegelsberger, Utpal Barman
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Patent number: 7716506Abstract: A system has a plurality of different clients. Each client generates a report signal indicative of a current latency tolerance associated with a performance state. A controller dynamically determines a power down level having a minimum power consumption capable of supporting the system latency of the configuration state of the clients.Type: GrantFiled: December 14, 2006Date of Patent: May 11, 2010Assignee: Nvidia CorporationInventors: Roman Surgutchik, Robert William Chapman, Edward L. Riegelsberger, Brad W. Simeral, Paul J. Gyugyi
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Publication number: 20100039149Abstract: According to an aspect of the present invention, one of multiple clock signals of different relative phases is selected based on a desired delay magnitude, and the digital values received on an input signal are then synchronized to an edge (“first edge”) of the selected clock signal to provide the digital values with the desired delay magnitude. In an embodiment, the selected clock signal can be delayed by a fine value (less than the minimum phase difference of the multiple clock signals) to provide a wide span of desired delays. An aspect of the invention provides for a synchronization circuit with reduced latency and which is substantially invariant to process, voltage and temperature (PVT) changes.Type: ApplicationFiled: August 12, 2008Publication date: February 18, 2010Applicant: NVIDIA CorporationInventors: Jyotirmaya Swain, Utpal Barman, Adarsh Kalliat, Raji Cherian, Edward L. Riegelsberger
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Publication number: 20100008158Abstract: Read leveling of memory units designed to receive access requests in a sequential chained topology writing a data pattern to the memory array. In an embodiment, a memory controller first writes a desired pattern into the memory array of a memory unit and then iteratively determines the accurate calibrated delay by setting a compensation delay to a test value, reading a data portion from the memory array based on the test value for the compensation delay, comparing the data portion with an expected data, determining that the test value is a calibrated compensation delay for the memory unit if the data portion equals the expected value.Type: ApplicationFiled: July 8, 2008Publication date: January 14, 2010Applicant: NVIDIA CORPORATIONInventors: Jyotirmaya Swain, Edward L. Riegelsberger, Utpal Barman
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Publication number: 20100008176Abstract: A memory controller provided according to an aspect of the present invention uses a slower clock signal during write leveling compared to when performing write operations thereafter. Due to such use of a slower clock signal, the various desired delays can be determined accurately and/or easily. In an embodiment, the frequency of the slower clock signal is determined based on the maximum fly-by delay (generally the delay between sending of a signal on the shared sequential path and the receipt at the memory unit in the sequence) that may be present in the memory system. For example, if the fly by delay can be M (an integer) times the time period of the clock signal during normal write operations, the slower clock signal may have a time period of M times that of the clock signal during write operation.Type: ApplicationFiled: July 9, 2008Publication date: January 14, 2010Applicant: NVIDIA CorporationInventors: Jyotirmaya Swain, Edward L. Riegelsberger, Utpal Barman
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Patent number: 7342590Abstract: Methods, circuits, and apparatus for reducing memory bandwidth used by a graphics processor. Uncompressed tiles are read from a display buffer portion of a graphics memory and received by an encoder. The uncompressed tiles are compressed and written back to the graphics memory. When a tile is needed again before it has been modified, the compressed version is read from memory, uncompressed, and displayed. To reduce the number of unnecessary writes of compressed tiles to memory, a tile is only written to memory if it has remained static for some number of refresh cycles. Also, to prevent a large number of compressed tiles being written to the display buffer in one refresh cycle, the encoder can be throttled after a number of tiles have been written. Validity information can be stored for use by a CRTC. If a tile is updated, the validity information is updated such that invalid compressed data is not read from memory and displayed.Type: GrantFiled: May 9, 2003Date of Patent: March 11, 2008Assignee: Nvidia CorporationInventors: John M. Danskin, Ziyad S. Hakura, Edward L. Riegelsberger, Jason M. Musicer, Stephen D. Lew