Patents by Inventor Edward W. Seibert

Edward W. Seibert has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8756554
    Abstract: A method comprises tracing a first and second terminal of a junction through a circuit layout to associated power supplies to determine their respective defined bias values. The method further comprises comparing the defined bias values of each terminal in order to determine, based on the comparison, whether the junction is forward biased.
    Type: Grant
    Filed: May 15, 2012
    Date of Patent: June 17, 2014
    Assignee: International Business Machines Corporation
    Inventors: Douglas W. Kemerer, Edward W. Seibert, Lijiang L. Wang
  • Publication number: 20130067425
    Abstract: A method comprises tracing a first and second terminal of a junction through a circuit layout to associated power supplies to determine their respective defined bias values. The method further comprises comparing the defined bias values of each terminal in order to determine, based on the comparison, whether the junction is forward biased.
    Type: Application
    Filed: May 15, 2012
    Publication date: March 14, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Douglas W. Kemerer, Edward W. Seibert, Lijiang L. Wang
  • Patent number: 8191030
    Abstract: A method comprises tracing a first and second terminal of a junction through a circuit layout to associated power supplies to determine their respective defined bias values. The method further comprises comparing the defined bias values of each terminal in order to determine, based on the comparison, whether the junction is forward biased.
    Type: Grant
    Filed: December 17, 2008
    Date of Patent: May 29, 2012
    Assignee: International Business Machines Corporation
    Inventors: Douglas W. Kemerer, Edward W. Seibert, Lijiang L. Wang
  • Publication number: 20090150842
    Abstract: A method comprises tracing a first and second terminal of a junction through a circuit layout to associated power supplies to determine their respective defined bias values. The method further comprises comparing the defined bias values of each terminal in order to determine, based on the comparison, whether the junction is forward biased.
    Type: Application
    Filed: December 17, 2008
    Publication date: June 11, 2009
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Douglas W. Kemerer, Edward W. Seibert, Lijiang L. Wang
  • Patent number: 7490303
    Abstract: A method comprises tracing a first and second terminal of a junction through a circuit layout to associated power supplies to determine their respective defined bias values. The method further comprises comparing the defined bias values of each terminal in order to determine, based on the comparison, whether the junction is forward biased.
    Type: Grant
    Filed: March 3, 2006
    Date of Patent: February 10, 2009
    Assignee: International Business Machines Corporation
    Inventors: Douglas W. Kemerer, Edward W. Seibert, Lijiang L. Wang
  • Patent number: 6519752
    Abstract: A method and structure for performing parasitic extraction for a multi-fingered device comprising of establishing a maximum processing width of a finger of the device, dividing fingers of the device that exceed the maximum width into sub-fingers, determining whether ones of the fingers and the sub-fingers have similar characteristics, combining ones of the fingers and the sub-fingers that have similar characteristics into combined fingers, and extracting parasitic values from the fingers, the sub-fingers and the combined fingers.
    Type: Grant
    Filed: April 28, 2000
    Date of Patent: February 11, 2003
    Assignee: International Business Machines Corporation
    Inventors: William C. Bakker, L. William Dewey, III, Peter A. Habitz, Judith H. McCullen, Edward W. Seibert, Michael J. Sullivan
  • Patent number: 6473887
    Abstract: A method and structure for performing capacitance extraction during the design of an integrated circuit includes inputting a specified wiring density and design requirements, determining a minimum spacing for wire segments based on the design requirements, calculating a transparency factor based on the wiring density, calculating a lateral capacitance assuming virtual wires are present in the integrated circuit, and calculating a vertical capacitance based on the transparency factor.
    Type: Grant
    Filed: April 27, 2000
    Date of Patent: October 29, 2002
    Assignee: International Business Machines Corporation
    Inventors: L. William Dewey, III, Peter A. Habitz, Edward W. Seibert
  • Patent number: 6430729
    Abstract: A method and structure for a method of determining characteristics of parasitic elements in an integrated circuit comprising, identifying manufacturing process parameters of devices in the integrated circuit, calculating a parasitic performance distribution for each of the devices based on the manufacturing process parameters, combining the parasitic performance distribution for each of the devices into a net parasitic value, and forming a parameterized model based on the net parasitic values.
    Type: Grant
    Filed: January 31, 2000
    Date of Patent: August 6, 2002
    Assignee: International Business Machines Corporation
    Inventors: L. William Dewey, Peter A. Habitz, Judith H. McCullen, Edward W. Seibert
  • Patent number: 5761080
    Abstract: According to the present embodiment, a method for calculating the parasitic capacitance in a semiconductor device is disclosed. According to the preferred method, a layout file containing the shapes of a semiconductor device is provided. The dimensions of the layout file are then adjusted to wafer dimensions so as reflect actual production devices. The shapes of the layout file are then partitioned into simpler shapes, typically abutted rectangles, called tiles. Each tile is then decomposed into overlap and fringe capacitance components, each component having a uniform capacitance environment with respect to its capacitance elements. The parasitic capacitance of the semiconductor device can thus be accurately computed, with an efficient use of resources. Additionally the preferred embodiment is easily adaptable to a wide range of technology types.
    Type: Grant
    Filed: November 22, 1995
    Date of Patent: June 2, 1998
    Assignee: International Business Machines Corporation
    Inventors: William F. DeCamp, John J. Ellis-Monaghan, Peter A. Habitz, Edward W. Seibert