Patents by Inventor Efraim Rotem

Efraim Rotem has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220407337
    Abstract: A hardware and/or software (e.g., a controller and/or firmware or software) that monitors a remaining capacity of a battery and adjusts a continuum of system performance settings ranging from best performance to best energy efficiency. The controller starts with best performance setting (at the expense of energy efficiency), and then the controller gradually shifts toward energy efficiency setting (at the expense of performance) when a battery usage exceeds a pre-defined drain rate (e.g., there is a deficit in the battery remaining capacity until the next charge). The controller reverts from energy efficiency setting towards high performance setting when the battery drain rate or discharge rate slows down (e.g., there is a surplus in the battery remaining capacity until the next charge).
    Type: Application
    Filed: June 22, 2021
    Publication date: December 22, 2022
    Applicant: Intel Corporation
    Inventors: Zhongsheng Wang, Chee Lim Nge, Sze Ling Yeap, Efraim Rotem, James Hermerding II, Ashraf Wadaa
  • Patent number: 11481013
    Abstract: In an embodiment, a processor includes processing cores, and a central control unit to: concurrently execute an outer control loop and an inner control loop, wherein the outer control loop is to monitor the processor as a whole, and wherein the inner control loop is to monitor a first processing core included in the processor; determine, based on the outer control loop, a first control action for the first processing core included in the processor; determine, based on the inner control loop, a second control action for the first processing core included in the processor; based on a comparison of the first control action and the second control action, select one of the first control action and the second control action as a selected control action; and apply the selected control action to the first processing core. Other embodiments are described and claimed.
    Type: Grant
    Filed: May 21, 2020
    Date of Patent: October 25, 2022
    Assignee: Intel Corporation
    Inventors: Doron Rajwan, Efraim Rotem, Eliezer Weissmann, Avinash N. Ananthakrishnan, Dorit Shapira
  • Publication number: 20220283619
    Abstract: In one embodiment, a processor includes a plurality of cores, at least two of which may execute redundantly, a configuration register to store a first synchronization domain indicator to indicate that a first core and a second core are associated with a first synchronization domain, and a power controller having a synchronization circuit to cause a dynamic adjustment to a frequency of at least one of the first and second cores to cause these cores to operate at a common frequency, based at least in part on the first synchronization domain indicator. Other embodiments are described and claimed.
    Type: Application
    Filed: May 26, 2022
    Publication date: September 8, 2022
    Inventors: Efraim Rotem, Eliezer Weissmann, Doron Rajwan, Nir Rosenzweig, Yoni Aizik
  • Patent number: 11435816
    Abstract: In one embodiment, a processor includes at least one core to execute instructions and a power controller coupled to the at least one core. The power controller may include a first logic to cause the at least one core to exit an idle state and enter into a maximum performance state for a first time duration, thereafter enter into an intermediate power state for a second time duration, and thereafter enter into a sustained performance state. Other embodiments are described and claimed.
    Type: Grant
    Filed: March 29, 2021
    Date of Patent: September 6, 2022
    Assignee: Intel Corporation
    Inventors: Efraim Rotem, Doron Rajwan, Eliezer Weissmann, Nir Rosenzweig, Eric Distefano, Ishmael F. Santos, James G. Hermerding, II
  • Patent number: 11436018
    Abstract: Systems, methods, and apparatuses relating to instructions to reset software thread runtime property histories in a hardware processor are described. In one embodiment, a hardware processor includes a hardware guide scheduler comprising a plurality of software thread runtime property histories; a decoder to decode a single instruction into a decoded single instruction, the single instruction having a field that identifies a model-specific register; and an execution circuit to execute the decoded single instruction to check that an enable bit of the model-specific register is set, and when the enable bit is set, to reset the plurality of software thread runtime property histories of the hardware guide scheduler.
    Type: Grant
    Filed: December 17, 2020
    Date of Patent: September 6, 2022
    Assignee: Intel Corporation
    Inventors: Eliezer Weissmann, Mark Charney, Michael Mishaeli, Robert Valentine, Itai Ravid, Jason W. Brandt, Gilbert Neiger, Baruch Chaikin, Efraim Rotem
  • Patent number: 11436118
    Abstract: An apparatus and method for intelligently scheduling threads across a plurality of logical processors.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: September 6, 2022
    Assignee: Intel Corporation
    Inventors: Eliezer Weissmann, Omer Barak, Rajshree Chabukswar, Russell Fenger, Eugene Gorbatov, Monica Gupta, Julius Mandelblat, Nir Misgav, Efraim Rotem, Ahmad Yasin
  • Patent number: 11402891
    Abstract: A processor includes a plurality of cores, at least two of which may execute redundantly, a configuration register to store a first synchronization domain indicator to indicate that a first core and a second core are associated with a first synchronization domain, and a power controller having a synchronization circuit to cause a dynamic adjustment to a frequency of at least one of the first and second cores to cause these cores to operate at a common frequency, based at least in part on the first synchronization domain indicator.
    Type: Grant
    Filed: March 24, 2021
    Date of Patent: August 2, 2022
    Assignee: Intel Corporation
    Inventors: Efraim Rotem, Eliezer Weissmann, Doron Rajwan, Nir Rosenzweig, Yoni Aizik
  • Publication number: 20220214737
    Abstract: In one embodiment, processor includes a first core to execute instructions, and a power controller to control power consumption of the processor. The power controller may include a hardware performance state controller to control a performance state of the first core autonomously to an operating system, and calculate a target operating frequency for the performance state based at least in part on an energy performance preference hint received from the operating system. Other embodiments are described and claimed.
    Type: Application
    Filed: March 28, 2022
    Publication date: July 7, 2022
    Inventors: Hisham ABU SALAH, Efraim ROTEM, Eliezer WEISSMANN, Yoni AIZIK, Daniel D. LEDERMAN
  • Publication number: 20220214738
    Abstract: Methods and apparatus relating to multi-level CPU (Central Processing Unit) high current protection are described. In one embodiment, different workloads may be assigned different license types and/or weights based on micro-architectural events (such as uop (micro-operation) types and sizes) and/or data types. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: March 28, 2022
    Publication date: July 7, 2022
    Applicant: Intel Corporation
    Inventors: Efraim Rotem, Nir Rosenzweig, Doron Rajwan, Alon Naveh, Eliezer Weissmann
  • Publication number: 20220197361
    Abstract: Apparatuses, methods and storage medium associated with current control for a multicore processor are disclosed herein. In embodiments, a multicore processor may include a plurality of analog current comparators, each analog current comparator to measure current utilization by a corresponding one of the cores of the multicore processor. The multicore processor may include one or more processors, devices, and/or circuitry to cause the cores to individually throttle based on measurements from the corresponding analog current comparators. In some embodiments, a memory device of the multicore processor may store instructions executable to operate a plurality power management agents to determine whether to send throttle requests based on a plurality of histories of the current measurements of the cores, respectively.
    Type: Application
    Filed: December 28, 2021
    Publication date: June 23, 2022
    Inventors: Alexander Gendler, Efraim Rotem, Nir Rosenzweig, Krishnakanth V. Sistla, Ashish V. Choubal, Ankush Varma
  • Publication number: 20220187893
    Abstract: Described are mechanisms and methods for tracking user behavior profile over large time intervals and extracting observations for a user usage profile. The mechanisms and methods use machine learning (ML) algorithms embedded into a dynamic platform and thermal framework (DPTF) (e.g., Dynamic Tuning Technology) and predict device workloads using hardware (HW) counters. These mechanisms and methods may accordingly increase performance and user responsiveness by dynamically changing an Energy Performance Preference (EPP) based on a longer time workload analysis and workload prediction.
    Type: Application
    Filed: July 14, 2020
    Publication date: June 16, 2022
    Inventors: Premanand SAKARDA, Efraim ROTEM, Eliezer WEISSMANN, Hisham ABU SALAH, Hadas BEJA, Russell FENGER, Deepak GANAPATHY, James HERMERDING, II, Ido KARAVANY, Nivedha KRISHNAKUMAR, Sudheer NAIR, Gilad OLSWANG, Moran PERI, Avishai WAGNER, Zhongsheng WANG, Noha YASSIN
  • Publication number: 20220179473
    Abstract: Techniques and mechanisms for transparently transitioning an interconnect fabric between a first frequency and a second frequency. In an embodiment, the fabric is coupled to an end point device via an asynchronous device. One or more nodes of the fabric operate in a first clock domain based on a clock signal, while the end point device operates in a different clock domain. Controller circuitry changes a frequency of the clock signal by stalling the clock signal throughout a first period of time which is greater than a duration of three cycles of a lower one of the first frequency or the second frequency. After the first period of time, cycling of the clock signal is provided at the second frequency. In another embodiment, the asynchronous device enables the frequency change without preventing communication with the end point device.
    Type: Application
    Filed: May 22, 2020
    Publication date: June 9, 2022
    Applicant: Intel Corporation
    Inventors: Chen Ranel, Christopher J. Lake, Hem Doshi, Ido Melamed, Vijay Degalahal, Yevgeni Sabin, Reena Patel, Yoav Ben-Raphael, Nimrod Angel, Efraim Rotem, Shaun Conrad, Tomer Ziv, Nir Rosenzweig, Esfir Natanzon, Yoni Aizik, Arik Gihon, Natanel Abitan
  • Publication number: 20220179808
    Abstract: Systems, methods, and apparatuses relating to hardware control of processor performance levels are described. In one embodiment, a processor includes a plurality of logical processing elements; and a power management circuit to change a highest non-guaranteed performance level and a highest guaranteed performance level for each of the plurality of logical processing elements, and set a notification in a status register when the highest non-guaranteed performance level is changed to a new highest non-guaranteed performance level.
    Type: Application
    Filed: November 16, 2021
    Publication date: June 9, 2022
    Inventors: Eliezer WEISSMANN, Efraim ROTEM, Doron RAJWAN, Hisham ABU SALAH, Ariel GUR, Guy M. THERIEN, Russell J. FENGER
  • Patent number: 11354213
    Abstract: In an embodiment, a processor includes multiple processing engines and a power control unit. The power control unit is to: maintain a first utilization metric for a first processing engine; detect a thread transfer from a first processing engine to a second processing engine; and generate, using the first utilization metric for the first processing engine, a second utilization metric for a second processing engine. Other embodiments are described and claimed.
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: June 7, 2022
    Assignee: Intel Corporation
    Inventors: Hisham Abu Salah, Arthur Leonard Brown, Russell J. Fenger, Deepak Samuel Kirubakaran, Asit K. Mallick, Jun Pan, Srinivas Pandruvada, Efraim Rotem, Arjan Van De Ven, Eliezer Weissmann, Rafal J. Wysocki
  • Patent number: 11340687
    Abstract: In one embodiment, processor includes a first core to execute instructions, and a power controller to control power consumption of the processor. The power controller may include a hardware performance state controller to control a performance state of the first core autonomously to an operating system, and calculate a target operating frequency for the performance state based at least in part on an energy performance preference hint received from the operating system. Other embodiments are described and claimed.
    Type: Grant
    Filed: March 16, 2021
    Date of Patent: May 24, 2022
    Assignee: Intel Corporation
    Inventors: Hisham Abu Salah, Efraim Rotem, Eliezer Weissmann, Yoni Aizik, Daniel D. Lederman
  • Patent number: 11307628
    Abstract: Methods and apparatus relating to multi-level CPU (Central Processing Unit) high current protection are described. In one embodiment, different workloads may be assigned different license types and/or weights based on micro-architectural events (such as uop (micro-operation) types and sizes) and/or data types. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: May 8, 2017
    Date of Patent: April 19, 2022
    Assignee: INTEL CORPORATION
    Inventors: Efraim Rotem, Nir Rosenzweig, Doron Rajwan, Alon Naveh, Eliezer Weissmann
  • Patent number: 11287871
    Abstract: For one disclosed embodiment, a processor comprises a plurality of processor cores to operate at variable performance levels. One of the plurality of processor cores may operate at one time at a performance level different than a performance level at which another one of the plurality of processor cores may operate at the one time. The plurality of processor cores are in a same package. Logic of the processor is to set one or more operating parameters for one or more of the plurality of processor cores. Logic of the processor is to monitor activity of one or more of the plurality of processor cores. Logic of the processor is to constrain power of one or more of the plurality of processor cores based at least in part on the monitored activity. The logic to constrain power is to limit a frequency at which one or more of the plurality of processor cores may be set. Other embodiments are also disclosed.
    Type: Grant
    Filed: July 2, 2018
    Date of Patent: March 29, 2022
    Assignee: Intel Corporation
    Inventors: Efraim Rotem, Oren Lamdan, Alon Naveh
  • Patent number: 11243768
    Abstract: Disclosed embodiments relate to processing logic for performing function operations. In one example, and apparatus includes an execution unit within a processor to execute a code block, power management hardware coupled to the execution unit, wherein the power management hardware is to monitor a first execution of the code block, store a micro-architectural context of the processor in a metadata block associated with the code block, the micro-architectural context including performance data resulting from the first execution of the code block, the performance data comprising power and energy usage data, and power management related parameters, read the associated metadata block upon a second execution of the code block, and tune the second execution based on the performance data stored in the associated metadata block to increase efficiency of executing the code block.
    Type: Grant
    Filed: January 28, 2019
    Date of Patent: February 8, 2022
    Assignee: Intel Corporation
    Inventors: Efraim Rotem, Eliezer Weissmann, Boris Ginzburg, Alon Naveh, Nadav Shulman, Ronny Ronen
  • Patent number: 11237615
    Abstract: Apparatuses, methods and storage medium associated with current control for a multicore processor are disclosed herein. In embodiments, a multicore processor may include a plurality of analog current comparators, each analog current comparator to measure current utilization by a corresponding one of the cores of the multicore processor. The multicore processor may include one or more processors, devices, and/or circuitry to cause the cores to individually throttle based on measurements from the corresponding analog current comparators. In some embodiments, a memory device of the multicore processor may store instructions executable to operate a plurality power management agents to determine whether to send throttle requests based on a plurality of histories of the current measurements of the cores, respectively.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: February 1, 2022
    Assignee: Intel Corporation
    Inventors: Alexander Gendler, Efraim Rotem, Nir Rosenzweig, Krishnakanth V. Sistla, Ashish V. Choubal, Ankush Varma
  • Patent number: 11221857
    Abstract: The present invention relates to a platform power management scheme. In some embodiments, a platform provides a relative performance scale using one or more parameters to be requested by an OSPM system.
    Type: Grant
    Filed: April 18, 2019
    Date of Patent: January 11, 2022
    Assignee: Intel Corporation
    Inventors: Guy M. Therien, Paul S. Diefenbaugh, Anil Aggarwal, Andrew D. Henroid, Jeremy J. Shrall, Efraim Rotem, Krishnakanth V. Sistla, Eliezer Weissmann