Patents by Inventor Ehren Mannebach
Ehren Mannebach has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11437405Abstract: Embodiments herein describe techniques for an integrated circuit (IC). The IC may include a first transistor, an insulator layer above the first transistor, and a second transistor above the insulator layer. The first transistor may be a p-type transistor including a channel in a substrate, a first source electrode, and a first drain electrode. A first metal contact may be coupled to the first source electrode, while a second metal contact may be coupled to the first drain electrode. The insulator layer may be next to the first metal contact, and next to the second metal contact. The second transistor may include a second source electrode, and a second drain electrode. The second source electrode may be coupled to the first metal contact, or the second drain electrode may be coupled to the second metal contact. Other embodiments may be described and/or claimed.Type: GrantFiled: June 29, 2018Date of Patent: September 6, 2022Assignee: Intel CorporationInventors: Gilbert Dewey, Patrick Morrow, Aaron Lilak, Willy Rachmady, Anh Phan, Ehren Mannebach, Hui Jae Yoo, Abhishek Sharma, Van H. Le, Cheng-Ying Huang
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Patent number: 11437283Abstract: Backside contact structures include etch selective materials to facilitate backside contact formation. An integrated circuit structure includes a frontside contact region, a device region below the frontside contact region, and a backside contact region below the device region. The device region includes a transistor. The backside contact region includes a first dielectric material under a source or drain region of the transistor, a second dielectric material laterally adjacent to the first dielectric material and under a gate structure of the transistor. A non-conductive spacer is between the first and second dielectric materials. The first and second dielectric materials are selectively etchable with respect to one another and the spacer. The backside contact region may include an interconnect feature that, for instance, passes through the first dielectric material and contacts a bottom side of the source/drain region, and/or passes through the second dielectric material and contacts the gate structure.Type: GrantFiled: March 15, 2019Date of Patent: September 6, 2022Assignee: Intel CorporationInventors: Aaron D. Lilak, Ehren Mannebach, Anh Phan, Richard E. Schenker, Stephanie A. Bojarski, Willy Rachmady, Patrick R. Morrow, Jeffery D. Bielefeld, Gilbert Dewey, Hui Jae Yoo
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Patent number: 11424160Abstract: In some embodiments, a semiconductor device structure is formed by using an angled etch to remove material so as to expose a portion of an adjacent conductor. The space formed upon removing the material can then be filled with a conductive material during formation of a contact or other conductive structure (e.g., and interconnection). In this way, the contact formation also fills the space to form an angled local interconnect portion that connects adjacent structures (e.g., a source/drain contact to an adjacent source/drain contact, a source/drain contact to an adjacent gate contact, a source/drain contact to an adjacent device level conductor also connected to a gate/source/drain contact). In other embodiments, an interconnection structure herein termed a “jogged via” establishes and electrical connection from laterally adjacent peripheral surfaces of conductive structures that are not coaxially or concentrically aligned with one another.Type: GrantFiled: February 13, 2019Date of Patent: August 23, 2022Assignee: Intel CorporationInventors: Aaron D. Lilak, Ehren Mannebach, Anh Phan, Richard Schenker, Stephanie A. Bojarski, Willy Rachmady, Patrick Morrow, Jeffery Bielefeld, Gilbert Dewey, Hui Jae Yoo, Nafees Kabir
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Publication number: 20220262796Abstract: Gate-all-around integrated circuit structures having depopulated channel structures, and methods of fabricating gate-all-around integrated circuit structures having depopulated channel structures using a selective bottom-up approach, are described. For example, an integrated circuit structure includes a vertical arrangement of nanowires above a substrate. The vertical arrangement of nanowires has one or more active nanowires above one or more oxide nanowires. A first gate stack is over and around the one or more active nanowires. A second gate stack is over and around the one or more oxide nanowires.Type: ApplicationFiled: April 27, 2022Publication date: August 18, 2022Inventors: Nicole THOMAS, Ehren MANNEBACH, Cheng-Ying HUANG, Marko RADOSAVLJEVIC
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Publication number: 20220246608Abstract: Stacked transistor structures having a conductive interconnect between upper and lower transistors. In an embodiment, the interconnect is formed by first provisioning a protective layer over an area to be protected (gate dielectric or other sensitive material) of upper transistor, and then etching material adjacent and below the protected area to expose an underlying contact point of lower transistor. A metal is deposited into the void created by the etch to provide the interconnect. The protective layer is resistant to the etch process and is preserved in the structure, and in some cases may be utilized as a work-function metal. In an embodiment, the protective layer is formed by deposition of reactive semiconductor and metal material layers which are subsequently transformed into a work function metal or work function metal-containing compound. A remnant of unreacted reactive semiconductor material may be left in structure and collinear with protective layer.Type: ApplicationFiled: April 21, 2022Publication date: August 4, 2022Inventors: Aaron D. LILAK, Anh PHAN, Ehren MANNEBACH, Cheng-Ying HUANG, Stephanie A. BOJARSKI, Gilbert DEWEY, Orb ACTON, Willy RACHMADY
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Patent number: 11380684Abstract: Stacked transistor structures including one or more thin film transistor (TFT) material nanowire or nanoribbon channel regions and methods of forming same are disclosed. In an embodiment, a second transistor structure has a TFT material nanowire or nanoribbon stacked on a first transistor structure which also includes nanowires or nanoribbons comprising TFT material or group IV semiconductor. The top and bottom channel regions may be configured the same or differently, with respect to shape and/or semiconductor materials. Top and bottom transistor structures (e.g., NMOS/PMOS) may be formed using the top and bottom channel region structures. An insulator region may be interposed between the upper and lower channel regions.Type: GrantFiled: September 28, 2018Date of Patent: July 5, 2022Assignee: Intel CorporationInventors: Gilbert Dewey, Aaron Lilak, Cheng-Ying Huang, Jack Kavalieros, Willy Rachmady, Anh Phan, Ehren Mannebach, Abhishek Sharma, Patrick Morrow, Hui Jae Yoo
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Patent number: 11374004Abstract: Stacked transistor structures and methods of forming same. In an embodiment, a stacked transistor structure has a wide central pedestal region and at least one relatively narrower channel region above and/or below the wider central pedestal region. The upper and lower channel regions are configured with a non-planar architecture, and include one or more semiconductor fins, nanowires, and/or nanoribbons. The top and bottom channel regions may be configured the same or differently, with respect to shape and/or semiconductor materials. In some cases, an outermost sidewall of one or both the top and/or bottom channel region structures, is collinear with an outermost sidewall of the wider central pedestal region. In some such cases, the outermost sidewall of the top channel region structure is collinear with the outermost sidewall of the bottom channel region structure. Top and bottom transistor structures (NMOS/PMOS) may be formed using the top and bottom channel region structures.Type: GrantFiled: June 29, 2018Date of Patent: June 28, 2022Assignee: Intel CorporationInventors: Aaron D. Lilak, Rishabh Mehandru, Anh Phan, Gilbert Dewey, Willy Rachmady, Stephen M. Cea, Sayed Hasan, Kerryann M. Foley, Patrick Morrow, Colin D. Landon, Ehren Mannebach
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Patent number: 11367684Abstract: Embodiments include an interconnect structure and methods of forming an interconnect structure. In an embodiment, the interconnect structure comprises a semiconductor substrate and an interlayer dielectric (ILD) over the semiconductor substrate. In an embodiment, an interconnect layer is formed over the ILD. In an embodiment, the interconnect layer comprises a first interconnect and a second interconnect. In an embodiment the interconnect structure comprises an electrically insulating plug that separates the first interconnect and the second interconnect. In an embodiment an uppermost surface of the electrically insulating plug is above an uppermost surface of the interconnect layer.Type: GrantFiled: May 21, 2018Date of Patent: June 21, 2022Assignee: Intel CorporationInventors: Ehren Mannebach, Kevin Lin, Richard Vreeland
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Patent number: 11367722Abstract: A nanowire transistor structure has a first device region with a first body of semiconductor material having a first cross-sectional shape. A second device region has a second body with a second cross-sectional shape different from the first cross-sectional shape. The first device section is vertically above or below the second device section with the bodies extending horizontally between a source and drain. A first gate structure is wrapped around the first body and a second gate structure is wrapped around the second body. Differences in the geometries of the nanowires can be used to optimize performance in the first device section independently of the second device section.Type: GrantFiled: September 21, 2018Date of Patent: June 21, 2022Assignee: Intel CorporationInventors: Aaron Lilak, Stephen Cea, Gilbert Dewey, Willy Rachmady, Roza Kotlyar, Rishabh Mehandru, Sean Ma, Ehren Mannebach, Anh Phan, Cheng-Ying Huang
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Patent number: 11348919Abstract: Gate-all-around integrated circuit structures having depopulated channel structures, and methods of fabricating gate-all-around integrated circuit structures having depopulated channel structures using a selective bottom-up approach, are described. For example, an integrated circuit structure includes a vertical arrangement of nanowires above a substrate. The vertical arrangement of nanowires has one or more active nanowires above one or more oxide nanowires. A first gate stack is over and around the one or more active nanowires. A second gate stack is over and around the one or more oxide nanowires.Type: GrantFiled: June 25, 2020Date of Patent: May 31, 2022Assignee: Intel CorporationInventors: Nicole Thomas, Ehren Mannebach, Cheng-Ying Huang, Marko Radosavljevic
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Patent number: 11348916Abstract: Stacked transistor structures having a conductive interconnect between upper and lower transistors. In an embodiment, the interconnect is formed by first provisioning a protective layer over an area to be protected (gate dielectric or other sensitive material) of upper transistor, and then etching material adjacent and below the protected area to expose an underlying contact point of lower transistor. A metal is deposited into the void created by the etch to provide the interconnect. The protective layer is resistant to the etch process and is preserved in the structure, and in some cases may be utilized as a work-function metal. In an embodiment, the protective layer is formed by deposition of reactive semiconductor and metal material layers which are subsequently transformed into a work function metal or work function metal-containing compound. A remnant of unreacted reactive semiconductor material may be left in structure and collinear with protective layer.Type: GrantFiled: June 29, 2018Date of Patent: May 31, 2022Assignee: Intel CorporationInventors: Aaron D. Lilak, Anh Phan, Ehren Mannebach, Cheng-Ying Huang, Stephanie A. Bojarski, Gilbert Dewey, Orb Acton, Willy Rachmady
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Patent number: 11342227Abstract: One of a source, drain or gate terminal of an upper-level transistor structure is coupled to one of a source, drain or gate terminal of a lower-level transistor structure through an asymmetrical interconnect having a lateral width that increases within a dimension parallel to a semiconductor sidewall of the upper-level transistor by a greater amount than in an orthogonal dimension.Type: GrantFiled: March 27, 2020Date of Patent: May 24, 2022Assignee: Intel CorporationInventors: Aaron Lilak, Ehren Mannebach, Nafees Kabir, Patrick Morrow, Gilbert Dewey, Willy Rachmady, Anh Phan
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Publication number: 20220102346Abstract: Embodiments disclosed herein include a semiconductor device. In an embodiment, the semiconductor device comprises a first transistor strata. The first transistor strata comprises a first backbone, a first transistor adjacent to a first edge of the first backbone, and a second transistor adjacent to a second edge of the first backbone. In an embodiment, the semiconductor device further comprises a second transistor strata over the first transistor strata. The second transistor strata comprises a second backbone, a third transistor adjacent to a first edge of the second backbone, and a fourth transistor adjacent to a second edge of the second backbone.Type: ApplicationFiled: December 9, 2021Publication date: March 31, 2022Inventors: Aaron D. LILAK, Rishabh MEHANDRU, Ehren MANNEBACH, Patrick MORROW, Willy RACHMADY
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Patent number: 11239236Abstract: Embodiments disclosed herein include a semiconductor device. In an embodiment, the semiconductor device comprises a first transistor strata. The first transistor strata comprises a first backbone, a first transistor adjacent to a first edge of the first backbone, and a second transistor adjacent to a second edge of the first backbone. In an embodiment, the semiconductor device further comprises a second transistor strata over the first transistor strata. The second transistor strata comprises a second backbone, a third transistor adjacent to a first edge of the second backbone, and a fourth transistor adjacent to a second edge of the second backbone.Type: GrantFiled: March 23, 2020Date of Patent: February 1, 2022Assignee: Intel CorporationInventors: Aaron D. Lilak, Rishabh Mehandru, Ehren Mannebach, Patrick Morrow, Willy Rachmady
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Publication number: 20210408246Abstract: Embodiments disclosed herein include transistor devices and methods of making such devices. In an embodiment, the transistor device comprises a stack of semiconductor channels with a first source/drain region on a first end of the semiconductor channels and a second source/drain region on a second end of the semiconductor channels. In an embodiment, the first source/drain region and the second source/drain region have a top surface and a bottom surface. In an embodiment, the transistor device further comprises a first source/drain contact electrically coupled to the top surface of the first source/drain region, and a second source/drain contact electrically coupled to the bottom surface of the second source/drain region. In an embodiment, the second source/drain contact is separated from the second source/drain region by an interfacial layer.Type: ApplicationFiled: June 25, 2020Publication date: December 30, 2021Inventors: Koustav GANGULY, Ryan KEECH, Subrina RAFIQUE, Glenn A. GLASS, Anand S. MURTHY, Ehren MANNEBACH, Mauro KOBRINSKY, Gilbert DEWEY
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Publication number: 20210407997Abstract: Gate-all-around integrated circuit structures having depopulated channel structures, and methods of fabricating gate-all-around integrated circuit structures having depopulated channel structures using a selective bottom-up approach, are described. For example, an integrated circuit structure includes a vertical arrangement of nanowires above a substrate. The vertical arrangement of nanowires has one or more active nanowires above one or more oxide nanowires. A first gate stack is over and around the one or more active nanowires. A second gate stack is over and around the one or more oxide nanowires.Type: ApplicationFiled: June 25, 2020Publication date: December 30, 2021Inventors: Nicole THOMAS, Ehren MANNEBACH, Cheng-Ying HUANG, Marko RADOSAVLJEVIC
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Publication number: 20210407999Abstract: Embodiments disclosed herein include stacked forksheet transistor devices, and methods of fabricating stacked forksheet transistor devices. In an example, an integrated circuit structure includes a backbone. A first transistor device includes a first vertical stack of semiconductor channels adjacent to an edge of the backbone. A second transistor device includes a second vertical stack of semiconductor channels adjacent to the edge of the backbone. The second transistor device is stacked on the first transistor device.Type: ApplicationFiled: June 26, 2020Publication date: December 30, 2021Inventors: Cheng-Ying HUANG, Gilbert DEWEY, Anh PHAN, Nicole K. THOMAS, Urusa ALAAN, Seung Hoon SUNG, Christopher M. NEUMANN, Willy RACHMADY, Patrick MORROW, Hui Jae YOO, Richard E. SCHENKER, Marko RADOSAVLJEVIC, Jack T. KAVALIEROS, Ehren MANNEBACH
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Publication number: 20210305098Abstract: Integrated circuitry comprising stacked first and second transistor structures. One of a source, drain or gate terminal of an upper-level transistor structure is coupled to one of a source, drain or gate terminal of a lower-level transistor structure through an asymmetrical interconnect having a lateral width that increases within a dimension parallel to a semiconductor sidewall of the upper-level transistor by a greater amount than in an orthogonal dimension. A dielectric material between the upper and lower transistor structures may be anisotropically etched asymmetrically by orienting a workpiece to be non-orthogonal to a reactive ion flux. Varying an angle between the reactive ion flux and a plane of the second transistor during an etch of the dielectric material may ensure an etched opening is of sufficient bottom dimension to expose a terminal of the lower-level transistor even if not perfectly aligned with the second transistor structure.Type: ApplicationFiled: March 27, 2020Publication date: September 30, 2021Applicant: Intel CorporationInventors: Aaron Lilak, Ehren Mannebach, Nafees Kabir, Patrick Morrow, Gilbert Dewey, Willy Rachmady, Anh Phan
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Publication number: 20210296315Abstract: Embodiments disclosed herein include a semiconductor device. In an embodiment, the semiconductor device comprises a first transistor strata. The first transistor strata comprises a first backbone, a first transistor adjacent to a first edge of the first backbone, and a second transistor adjacent to a second edge of the first backbone. In an embodiment, the semiconductor device further comprises a second transistor strata over the first transistor strata. The second transistor strata comprises a second backbone, a third transistor adjacent to a first edge of the second backbone, and a fourth transistor adjacent to a second edge of the second backbone.Type: ApplicationFiled: March 23, 2020Publication date: September 23, 2021Inventors: Aaron D. LILAK, Rishabh MEHANDRU, Ehren MANNEBACH, Patrick MORROW, Willy RACHMADY
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Publication number: 20200411511Abstract: A device is disclosed. The device includes a first semiconductor fin, a first source-drain epitaxial region adjacent a first portion of the first semiconductor fin, a second source-drain epitaxial region adjacent a second portion of the first semiconductor fin, a first gate conductor above the first semiconductor fin, a gate spacer covering the sides of the gate conductor, a second semiconductor fin below the first semiconductor fin, a second gate conductor on a first side of the second semiconductor fin and a third gate conductor on a second side of the second semiconductor fin, a third source-drain epitaxial region adjacent a first portion of the second semiconductor fin, and a fourth source-drain epitaxial region adjacent a second portion of the second semiconductor fin. The device also includes a dielectric isolation structure below the first semiconductor fin and above the second semiconductor fin that separates the first semiconductor fin and the second semiconductor fin.Type: ApplicationFiled: June 27, 2019Publication date: December 31, 2020Inventors: Willy RACHMADY, Cheng-Ying HUANG, Gilbert DEWEY, Aaron LILAK, Patrick MORROW, Anh PHAN, Ehren MANNEBACH, Jack T. KAVALIEROS