Abstract: A three dimensional non-volatile memory structure includes word lines connected to non-volatile memory cells arranged in blocks. A plurality of word line switches are connected to the word lines and one or more sources of voltage. The word line switches are arranged in groups of X word line switches such that each group of X word line switches is positioned in a line under Y blocks of non-volatile memory cells and has a length that is equal to the width of the Y blocks of non-volatile memory cells. To allow closer placement of word line switches that supply different blocks and support the possible large voltage differences between their transistors, word line switches supplying different blocks are formed over a single active region and separated by an intermediate control gate set to be off.

Abstract: A field effect transistor includes a gate dielectric and a gate electrode overlying an active region and contacting a sidewall of a trench isolation structure. The transistor may be a fringeless transistor in which the gate electrode does not overlie a portion of the trench isolation region. A planar dielectric spacer plate and a conductive gate cap structure may overlie the gate electrode. The conductive gate cap structure may have a z-shaped vertical cross-sectional profile to contact the gate electrode and to provide a segment overlying the planar dielectric spacer plate. Alternatively or additionally, a conductive gate connection structure may be provided to provide electrical connection between two electrodes of adjacent field effect transistors.

Abstract: A field effect transistor includes a gate dielectric and a gate electrode overlying an active region and contacting a sidewall of a trench isolation structure. The transistor may be a fringeless transistor in which the gate electrode does not overlie a portion of the trench isolation region. A planar dielectric spacer plate and a conductive gate cap structure may overlie the gate electrode. The conductive gate cap structure may have a z-shaped vertical cross-sectional profile to contact the gate electrode and to provide a segment overlying the planar dielectric spacer plate. Alternatively or additionally, a conductive gate connection structure may be provided to provide electrical connection between two electrodes of adjacent field effect transistors.

Abstract: A field effect transistor includes a gate dielectric and a gate electrode overlying an active region and contacting a sidewall of a trench isolation structure. The transistor may be a fringeless transistor in which the gate electrode does not overlie a portion of the trench isolation region. A planar dielectric spacer plate and a conductive gate cap structure may overlie the gate electrode. The conductive gate cap structure may have a z-shaped vertical cross-sectional profile to contact the gate electrode and to provide a segment overlying the planar dielectric spacer plate. Alternatively or additionally, a conductive gate connection structure may be provided to provide electrical connection between two electrodes of adjacent field effect transistors.

Abstract: A semiconductor structure includes a field effect transistor located on a semiconductor substrate, a silicon oxide liner contacting at least a portion of the semiconductor substrate, a silicon nitride liner contacting a top surface and a sidewall of the silicon oxide liner and contacting a top surface of the semiconductor substrate in a seal region, a silicon nitride diffusion barrier layer including a planar bottom surface that contacts top surfaces of vertically extending portions of the silicon nitride liner, and a silicon oxide material portion overlying the silicon nitride diffusion barrier layer. A combination of the silicon nitride liner and the silicon nitride diffusion barrier layer constitutes a hydrogen diffusion barrier structure that continuously extends from the seal region and over the field effect transistor.

Abstract: An integrated circuit connection structure includes a contact plug extending vertically in a first dielectric, a conductive line formed of a metal extending horizontally in the first dielectric, and a contact plug extension that extends between a top surface of the contact plug and the conductive line. The plug extension is formed of the metal, has a bottom surface that lies in contact with the top surface of the contact plug, and is bounded on at least one side by a portion of a second dielectric material.

Abstract: A NAND flash memory integrated circuit chip includes a cell area and a peripheral area with structures of different heights, with higher structures in the peripheral area to provide low resistance and lower structures in the memory array so that the risk of word line collapse is maintained at acceptable levels.

Abstract: A NAND flash memory integrated circuit chip includes a cell area and a peripheral area with structures of different heights, with higher structures in the peripheral area to provide low resistance and lower structures in the memory array so that the risk of word line collapse is maintained at acceptable levels.

Abstract: A method of manufacturing a semiconductor device includes a process of removing, by dry etching, an insulating layer which is formed on the top surface of a Ni-containing silicide layer to thereby at least partially expose the Ni-containing silicide layer; and a process of cleaning the exposed portion of the Ni-containing silicide layer using reduced water having a reductive function.

Abstract: A method of manufacturing a semiconductor device includes a process of removing, by dry etching, an insulating layer which is formed on the top surface of a Ni-containing silicide layer to thereby at least partially expose the Ni-containing silicide layer; and a process of cleaning the exposed portion of the Ni-containing silicide layer using reduced water having a reductive function.