Abstract: A pillar delivery method is a method for delivering a plurality of pillars onto a substrate, including a glass panel, to manufacture a glass panel unit. The pillar delivery method includes an irradiation step, a holding step, and a mounting step. The irradiation step includes setting, over a holder, a sheet for use to form pillars and irradiating the sheet with a laser beam to punch out the plurality of pillars. The holding step includes having the plurality of pillars, which have been punched out of the sheet, held by the holder. The mounting step includes picking up some or all of the plurality of pillars from the holder and mounting the pillars onto the substrate.

Abstract: A method for manufacturing a glass panel unit includes an assembling step, a bonding step, a gas exhausting step, a sealing step, and an activating step. The bonding step includes melting a peripheral wall in a baking furnace at a first predetermined temperature to hermetically bond a first glass pane and a second glass pane together with the peripheral wall thus melted. The gas exhausting step includes exhausting a gas from an internal space through an exhaust port in the baking furnace to turn the internal space into a vacuum space. The sealing step includes locally heating to a temperature higher than a second predetermined temperature, and thereby melting, either a port sealing material or an exhaust pipe to seal the exhaust port and thereby obtain a work in progress. The activating step includes activating a gas adsorbent after the sealing step to obtain a glass panel unit.

Abstract: This disclosure relates to methods of reducing inflammation, angiogenesis, vascular leakage and neovascularization by administering to a subject in need thereof one or more stable analogs of CYP450 lipid metabolites (e.g., eicosanoids) and one or more inhibitors of a soluble epoxide hydrolase (sEH). This disclosure also relates to methods of treating disorders associated with inflammation, angiogenesis, vascular leakage and neovascularization by administering to a subject in need thereof one or more stable analogs of CYP450 lipid metabolites (e.g., eicosanoids) and one or more inhibitors of a soluble epoxide hydrolase (sEH). This disclosure further relates to pharmaceutical compositions and kits comprising at least one stable analog of CYP450 lipid metabolites (e.g., eicosanoids) and at least one inhibitor of a soluble epoxide hydrolase (sEH).

Abstract: This disclosure relates to methods of reducing inflammation, angiogenesis, vascular leakage and neovascularization by administering to a subject in need thereof one or more stable analogs of CYP450 lipid metabolites (e.g., eicosanoids) and one or more inhibitors of a soluble epoxide hydrolase (sEH). This disclosure also relates to methods of treating disorders associated with inflammation, angiogenesis, vascular leakage and neovascularization by administering to a subject in need thereof one or more stable analogs of CYP450 lipid metabolites (e.g., eicosanoids) and one or more inhibitors of a soluble epoxide hydrolase (sEH). This disclosure further relates to pharmaceutical compositions and kits comprising at least one stable analog of CYP450 lipid metabolites (e.g., eicosanoids) and at least one inhibitor of a soluble epoxide hydrolase (sEH).

Abstract: An oscillation detection circuit according to the present invention has a differential circuit by a bipolar transistor where oscillation output of an oscillation circuit is inputted; a capacitance element that is connected to an output terminal of this differential circuit and charges or discharges in response to potential of the output terminal; and a detection circuit that detects a desired oscillation state of an oscillation signal terminal based on potential of this capacitance element.

Abstract: To provide a voltage controlled oscillator having a large variable width of oscillation frequency while ensuring oscillation starting performance, a P-channel MOS transistor Tr is made ON by detecting that an oscillation signal is provided with a predetermined amplitude value and oscillating operation is shifted from an initial state to a steady state by a detecting circuit OPC and a capacitor CA is connected in series with a series circuit constituted by a crystal resonator XL and a varicap diode CV. In the initial state, a load capacitance is reduced to thereby cancel an amount of reducing conductance gm of an oscillation amplifying portion to correspond to operation of the crystal resonator by a low amplitude and negative resistance necessary for maintaining excellent oscillation starting performance is provided and in the steady state, a width of changing the oscillation frequency is enlarged by enhancing an effect of the varicap diode CV.

Abstract: An oscillation control circuit is offered which can improve the startability of an oscillator circuit operating at high frequencies and at a low power-supply voltage. When the oscillation potential of the oscillation signal is between the inversion potential (1.2 volts) of a CMOS inverter IV1 and the inversion potential (1.8 volts) of a CMOS inverter IV2, the logical output value of a CMOS Schmitt inverter SI1 is 1. The output of a CMOS inverter formed by MOS transistors T32 and T33 is shorted out via a MOS transistor T34. Its logical output value is kept at 1. When the inversion potential of the CMOS inverter IV1 or the inversion potential of the CMOS inverter IV2 is exceeded, if the input voltage to the CMOS Schmitt trigger SI1 increases above its inversion potential (1.8 volts), the logical output value assumes a value of 0. The CMOS inverter formed by the MOS transistors T12 and T13 is first set into operation. The oscillation signal is inverted, setting a circuit LA at a later stage into operation.

Abstract: An oscillator circuit adapted for a piezoelectric oscillator which has a weak oscillation output for generating high frequencies is provided. The speed of operation of the oscillator circuit is increased. An integrated circuit for such an oscillator circuit is also provided. The oscillator circuit has an amplifier portion consisting of CMOS inverters connected in cascade. MOS transistors forming the CMOS inverters have channel widths that decrease successively from the first stage to the last stage to improve the amplification factor of the amplifier portion at high frequencies. This makes it possible to amplify weak oscillation output from the quartz oscillator (XL). A filter circuit produces a peak of negative resistance at a frequency higher than conventional. This permit oscillation operation at higher frequencies.

Abstract: To provide a voltage controlled oscillator having a large variable width of oscillation frequency while ensuring oscillation starting performance, a P-channel MOS transistor Tr is made ON by detecting that an oscillation signal is provided with a predetermined amplitude value and oscillating operation is shifted from an initial state to a steady state by a detecting circuit OPC and a capacitor CA is connected in series with a series circuit constituted by a crystal resonator XL and a varicap diode CV. In the initial state, a load capacitance is reduced to thereby cancel an amount of reducing conductance gm of an oscillation amplifying portion to correspond to operation of the crystal resonator by a low amplitude and negative resistance necessary for maintaining excellent oscillation starting performance is provided and in the steady state, a width of changing the oscillation frequency is enlarged by enhancing an effect of the varicap diode CV.

Abstract: An oscillator circuit adapted for a piezoelectric oscillator which has a weak oscillation output for generating high frequencies is provided. The speed of operation of the oscillator circuit is increased. An integrated circuit for such an oscillator circuit is also provided. The oscillator circuit has an amplifier portion consisting of CMOS inverters connected in cascade. MOS transistors forming the CMOS inverters have channel widths that decrease successively from the first stage to the last stage to improve the amplification factor of the amplifier portion at high frequencies. This makes it possible to amplify weak oscillation output from the quartz oscillator (XL). A filter circuit produces a peak of negative resistance at a frequency higher than conventional. This permit oscillation operation at higher frequencies.

Abstract: An oscillation control circuit is offered which can improve the startability of an oscillator circuit operating at high frequencies and at a low power-supply voltage. When the oscillation potential of the oscillation signal is between the inversion potential (1.2 volts) of a CMOS inverter IV1 and the inversion potential (1.8 volts) of a CMOS inverter IV2, the logical output value of a CMOS Schmitt inverter SI1 is 1. The output of a CMOS inverter formed by MOS transistors T32 and T33 is shorted out via a MOS transistor T34. Its logical output value is kept at 1. When the inversion potential of the CMOS inverter IV1 or the inversion potential of the CMOS inverter IV2 is exceeded, if the input voltage to the CMOS Schmitt trigger SI1 increases above its inversion potential (1.8 volts), the logical output value assumes a value of 0. The CMOS inverter formed by the MOS transistors T12 and T13 is first set into operation. The oscillation signal is inverted, setting a circuit LA at a later stage into operation.

Abstract: In a quartz oscillation circuit, electric current flowing through a quartz oscillator is reduced. Resistors Rg and Rd are provided respectively in any of paths formed by an output terminal, a capacitance element Cd and a power supply terminal VDD of a CMOS inverter 2 and any of paths formed by an input terminal, a capacitance element Cg and a power supply terminal VDD, thereby reducing a current flowing through a quartz oscillator. In particular, the total value of the resistors Rd and Rg is determined in a range of from 10&OHgr; to 320&OHgr;, thereby reducing a quartz current and obtaining a required negative resistance.

Abstract: In a quartz oscillation circuit, electric current flowing through a quartz oscillator is reduced. Resistors Rg and Rd are provided respectively in any of paths formed by an output terminal, a capacitance element Cd and a power supply terminal VDD of a CMOS inverter 2 and any of paths formed by an input terminal, a capacitance element Cg and a power supply terminal VDD, thereby reducing a current flowing through a quartz oscillator. In particular, the total value of the resistors Rd and Rg is determined in a range of from 10 &OHgr; to 320 &OHgr;, thereby reducing a quartz current and obtaining a required negative resistance.

Abstract: A crystal oscillator circuit includes a CMOS invertor having an input terminal and an output terminal, a crystal resonator connected between the input terminal and the output terminal respectively at a first connection node and a second connection node, and a feedback resistor connected between the input terminal and the output terminal of the CMOS invertor. A first capacitor is provided between the first connection node and a power source terminal at a predetermined potential and a second capacitor is provided between the second connection node and a power source terminal at the predetermined potential. At least one resistor is disposed in series with at least one of the first capacitor and the second capacitor and has a resistance so as to limit a crystal current in the crystal resonator while maintaining negative resistance for stable oscillation. In an embodiment, a resistor is provided in series with each capacitor.

Abstract: A CMOS circuit prevents feedthrough current and has a small-scaled circuit constitution. An output stage has a P-channel MOS transistor and an N-channel MOS transistor with drains connected to each other to form an output terminal and gates respectively connected to output terminals of first and second series circuits. The first and second series circuits control supply of power and each includes an N-channel MOS transistor and a P-channel MOS transistor with drains connected together to form the output terminal and gates connected together to form an input terminal. A delay circuit receives an input signal and produces a delayed input signal which drives the input terminals of the first and second series circuits. P-channel and N-channel MOS transistors control power potentials applied to sources of the respective P-channel and N-channel MOS transistors of the second and first series circuits and are driven by the input signal which is applied to their gates.

Abstract: The output of the first CMOS inverter, connected as an oscillator, is applied to the inputs of second and third CMOS inverters that have logic threshold voltages higher and lower than the logic threshold voltage of the first inverter. The outputs of the second and third CMOS inverters are connected to an output circuit via a logic output circuit. The output of the logic output circuit is shorted by an output control circuit, under the control of the outputs of the second and third CMOS inverters, when the output of the oscillator is between the logic threshold voltages of the second and third inverters.

Abstract: A flexible replica grating having a metal layer of a wave-like shape, a synthetic resin layer for supporting the metal layer, and a flexible synthetic resin film for supporting the synthetic resin layer.

Abstract: A granular fixed molded article of an enzyme or microorganism strain is prepared by adding dropwise a liquid composition, composed of (a) a hydrophilic photocurable resin having at least two ethylenically unsaturated bonds per molecule, (b) a photopolymerization initiator, (c) a water-soluble high-molecular-weight polysaccharide having the ability to become a gel upon contact with at least one polyvalent metal ion and (d) an enzyme or microorganism strain, to an aqueous medium containing a polyvalent metal ion to gel the composition in a granular form, and then irradiating actinic light on the resulting granular gel to cure the photocurable resin in the granular gel.

Abstract: Continuous fermentation with yeast to produce alcohol is carried out by continuously passing a carbohydrate-containing substrate liquid through a vessel packed with a thin film means having yeast immobilized therein. Surfaces of the thin film means extend in the direction of flow within the vessel to provide elongated parallel passages. The thin film means occupies from 10 to 65% of the volume of the vessel and preferably has a thickness of 0.1 to 3 mm. Preferably, the thin film means is formed by mixing an aqueous yeast suspension with a photo-crosslinkable resin and subjecting the mixture to radiation to photo-crosslink the resin.

Abstract: Methods for copying optical information are disclosed. The methods comprise the steps of disposing a master mask with a tracking signal or other information recorded therein over an optical memory material comprised of heat mode recording material which can be thermally altered in order to deform or remove the material upon the application of an energy beam, permitting recording on the altered recording material and irradiating the master disk with flash light for a period of 1 microsecond or less, or in the alternative, scanning with a laser beam focused to a spot having a diameter of at least 10 .mu.m on the master mask with the exposure time at each area of the optical memory material being preferably 1 microsecond or less.