Patents by Inventor Eiichi Nakano

Eiichi Nakano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10600770
    Abstract: A semiconductor device assembly, including an interposer comprising a glass material, a semiconductor die comprising a proximity coupling on a side of the interposer, and at least one other semiconductor die comprising a proximity coupling configured for communicating signals with the proximity coupling of the semiconductor die, on an opposing side of the interposer. The assembly may optionally be configured for optical signal communication with higher level packaging. Semiconductor device packages, systems and methods of operation are also disclosed.
    Type: Grant
    Filed: May 14, 2018
    Date of Patent: March 24, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Eiichi Nakano, Shiro Uchiyama
  • Patent number: 10580720
    Abstract: A silicon interposer that includes an array, or pattern, of conductive paths positioned within a silicon substrate with a plurality of pins on the exterior of the substrate. Each of the pins is connected to a portion of the array of conductive paths. The array of conductive paths is configurable to provide a first electrical flow path through the substrate via a portion of the array of conductive paths or a second electrical flow path through the substrate. The electrical flow path through the substrate may be customizable for testing various die or chip layout designs. The electrical flow path through the substrate may be customizable by laser ablation of portions of the conductive paths, breaking of fuses along the conductive paths, and/or the actuation of logic gates connected to the conductive paths.
    Type: Grant
    Filed: October 22, 2018
    Date of Patent: March 3, 2020
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Bret K. Street, Owen R. Fay, Eiichi Nakano
  • Patent number: 10529659
    Abstract: Semiconductor devices having one or more vias filled with a transparent and electrically conductive material are disclosed herein. In one embodiment, a semiconductor device includes a first semiconductor die stacked over a second semiconductor die. The first semiconductor die can include at least one via that is axially aligned with a corresponding via of the second semiconductor die. The vias of the first and second semiconductor dies can be filled with a transparent and electrically conductive material that both electrically and optically couples the first and second semiconductor dies.
    Type: Grant
    Filed: November 7, 2018
    Date of Patent: January 7, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Eiichi Nakano, Mark E. Tuttle
  • Publication number: 20190385996
    Abstract: A semiconductor device assembly, including an interposer comprising a glass material, a semiconductor die comprising a proximity coupling on a side of the interposer, and at least one other semiconductor die comprising a proximity coupling configured for communicating signals with the proximity coupling of the semiconductor die, on an opposing side of the interposer. The assembly may optionally be configured for optical signal communication with higher level packaging. Semiconductor device packages, systems and methods of operation are also disclosed.
    Type: Application
    Filed: August 28, 2019
    Publication date: December 19, 2019
    Inventors: Eiichi Nakano, Shiro Uchiyama
  • Publication number: 20190348394
    Abstract: Methods of forming semiconductor device packages comprising stacking multiple dice, the die stack exhibiting thin bond lines and having an outer environmental coating, the bond lines and environmental coating comprising an in situ formed compound. Semiconductor device packages so formed and electronic systems incorporating such packages are also disclosed.
    Type: Application
    Filed: April 23, 2019
    Publication date: November 14, 2019
    Inventor: Eiichi Nakano
  • Publication number: 20190348406
    Abstract: A semiconductor device assembly, including an interposer comprising a glass material, a semiconductor die comprising a proximity coupling on a side of the interposer, and at least one other semiconductor die comprising a proximity coupling configured for communicating signals with the proximity coupling of the semiconductor die, on an opposing side of the interposer. The assembly may optionally be configured for optical signal communication with higher level packaging. Semiconductor device packages, systems and methods of operation are also disclosed.
    Type: Application
    Filed: May 14, 2018
    Publication date: November 14, 2019
    Inventors: Eiichi Nakano, Shiro Uchiyama
  • Patent number: 10446527
    Abstract: Semiconductor devices, systems including semiconductor devices, and methods of making and operating semiconductor devices. Such semiconductor devices can comprise a substrate, a first die mounted to the substrate, and a second die mounted to the first die in an offset position. The first die having first inductors at a first active side of the first die, the second inductors at a second active side of the second die, and a least one first inductor is proximate and inductively coupled to a second inductor. First interconnects electrically couple the substrate to the first die, and second interconnects electrically couple the second die to the substrate. The first interconnects extend from an upper surface of the substrate to the first active side, and the second interconnects extend from the second active side to the lower surface of the substrate.
    Type: Grant
    Filed: September 11, 2018
    Date of Patent: October 15, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Eiichi Nakano
  • Patent number: 10418255
    Abstract: Semiconductor device packages may include a support structure having electrical connections therein. Semiconductor device modules may be located on a surface of the support structure. A molding material may at least partially surround each semiconductor module on the surface of the support structure. A thermal management device may be operatively connected to the semiconductor device modules on a side of the semiconductor device modules opposite the support structure. At least some of the semiconductor device modules may include a stack of semiconductor dice, at least two semiconductor dice in the stack being secured to one another by diffusion of electrically conductive material of electrically conductive elements into one another.
    Type: Grant
    Filed: December 1, 2017
    Date of Patent: September 17, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Eiichi Nakano
  • Publication number: 20190273000
    Abstract: Semiconductor device packages may include a support structure having electrical connections therein. Semiconductor device modules may be located on a surface of the support structure. A molding material may at least partially surround each semiconductor module on the surface of the support structure. A thermal management device may be operatively connected to the semiconductor device modules on a side of the semiconductor device modules opposite the support structure. At least some of the semiconductor device modules may include a stack of semiconductor dice, at least two semiconductor dice in the stack being secured to one another by diffusion of electrically conductive material of electrically conductive elements into one another.
    Type: Application
    Filed: May 21, 2019
    Publication date: September 5, 2019
    Inventor: Eiichi Nakano
  • Publication number: 20190214331
    Abstract: A semiconductor device assembly that includes a flexible member having a first portion connected to a substrate and a connector attached to a second portion of the flexible member. The connector is electrically connected to the substrate via a conducting layer within the flexible member. The substrate may be a semiconductor device, such as a chip. The connector may be configured to connect the semiconductor device to another semiconductor device assembly or a system board, such as a printed circuit board. A material may encapsulate at least a portion of the substrate of the semiconductor assembly. The semiconductor device assembly may be formed by selectively connecting the flexible member to a first substrate. A second substrate and connector may then be connected to the flexible member. A release layer may be used to release the assembly of the second substrate, flexible member, and connector from the first substrate.
    Type: Application
    Filed: March 13, 2019
    Publication date: July 11, 2019
    Inventors: Chan H. Yoo, Eiichi Nakano
  • Publication number: 20190198443
    Abstract: Semiconductor devices having one or more vias filled with a transparent and electrically conductive material are disclosed herein. In one embodiment, a semiconductor device includes a first semiconductor die stacked over a second semiconductor die. The first semiconductor die can include at least one via that is axially aligned with a corresponding via of the second semiconductor die. The vias of the first and second semiconductor dies can be filled with a transparent and electrically conductive material that both electrically and optically couples the first and second semiconductor dies.
    Type: Application
    Filed: November 7, 2018
    Publication date: June 27, 2019
    Inventors: Eiichi Nakano, Mark E. Tuttle
  • Patent number: 10319696
    Abstract: Methods of forming semiconductor device packages comprising stacking multiple dice, the die stack exhibiting thin bond lines and having an outer environmental coating, the bond lines and environmental coating comprising an in situ formed compound. Semiconductor device packages so formed and electronic systems incorporating such packages are also disclosed.
    Type: Grant
    Filed: May 10, 2018
    Date of Patent: June 11, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Eiichi Nakano
  • Publication number: 20190172724
    Abstract: Semiconductor device packages may include a support structure having electrical connections therein. Semiconductor device modules may be located on a surface of the support structure. A molding material may at least partially surround each semiconductor module on the surface of the support structure. A thermal management device may be operatively connected to the semiconductor device modules on a side of the semiconductor device modules opposite the support structure. At least some of the semiconductor device modules may include a stack of semiconductor dice, at least two semiconductor dice in the stack being secured to one another by diffusion of electrically conductive material of electrically conductive elements into one another.
    Type: Application
    Filed: December 1, 2017
    Publication date: June 6, 2019
    Inventor: Eiichi Nakano
  • Patent number: 10276487
    Abstract: A semiconductor device assembly that includes a flexible member having a first portion connected to a substrate and a connector attached to a second portion of the flexible member. The connector is electrically connected to the substrate via a conducting layer within the flexible member. The substrate may be a semiconductor device, such as a chip. The connector may be configured to connect the semiconductor device to another semiconductor device assembly or a system board, such as a printed circuit board. A material may encapsulate at least a portion of the substrate of the semiconductor assembly. The semiconductor device assembly may be formed by selectively connecting the flexible member to a first substrate. A second substrate and connector may then be connected to the flexible member. A release layer may be used to release the assembly of the second substrate, flexible member, and connector from the first substrate.
    Type: Grant
    Filed: October 18, 2017
    Date of Patent: April 30, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Chan H. Yoo, Eiichi Nakano
  • Publication number: 20190115286
    Abstract: A semiconductor device assembly that includes a flexible member having a first portion connected to a substrate and a connector attached to a second portion of the flexible member. The connector is electrically connected to the substrate via a conducting layer within the flexible member. The substrate may be a semiconductor device, such as a chip. The connector may be configured to connect the semiconductor device to another semiconductor device assembly or a system board, such as a printed circuit board. A material may encapsulate at least a portion of the substrate of the semiconductor assembly. The semiconductor device assembly may be formed by selectively connecting the flexible member to a first substrate. A second substrate and connector may then be connected to the flexible member. A release layer may be used to release the assembly of the second substrate, flexible member, and connector from the first substrate.
    Type: Application
    Filed: October 18, 2017
    Publication date: April 18, 2019
    Inventors: Chan H. Yoo, Eiichi Nakano
  • Publication number: 20190067253
    Abstract: Semiconductor devices, systems including semiconductor devices, and methods of making and operating semiconductor devices. Such semiconductor devices can comprise a substrate, a first die mounted to the substrate, and a second die mounted to the first die in an offset position. The first die having first inductors at a first active side of the first die, the second inductors at a second active side of the second die, and a least one first inductor is proximate and inductively coupled to a second inductor. First interconnects electrically couple the substrate to the first die, and second interconnects electrically couple the second die to the substrate. The first interconnects extend from an upper surface of the substrate to the first active side, and the second interconnects extend from the second active side to the lower surface of the substrate.
    Type: Application
    Filed: September 11, 2018
    Publication date: February 28, 2019
    Inventor: Eiichi Nakano
  • Patent number: 10217726
    Abstract: Several embodiments of the present technology are directed to semiconductor devices, systems including semiconductor devices, and methods of making and operating semiconductor devices. In some embodiments, a semiconductor device comprises a substrate, a first die mounted to the substrate and including first inductors, and a second die mounted to the first die in an offset position and including second inductors. The first inductors are at an active side of the first die, and the second inductors are at an active side of the second die. At least a portion of the first inductors are proximate and inductively coupled to the second inductors. The semiconductor device further comprises a first plurality of interconnects electrically coupling the substrate to the first die, and a second plurality of interconnects electrically coupling the second die to the substrate.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: February 26, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Eiichi Nakano
  • Patent number: 10177120
    Abstract: Several embodiments of the present technology are directed to semiconductor devices, systems including semiconductor devices, and methods of making and operating semiconductor devices. In some embodiments, a semiconductor device comprises a substrate, a first die mounted to the substrate and including first inductors, and a second die mounted to the first die in an offset position and including second inductors. The first inductors are at an active side of the first die, and the second inductors are at an active side of the second die. At least a portion of the first inductors are proximate and inductively coupled to the second inductors. The semiconductor device further comprises a first plurality of interconnects electrically coupling the substrate to the first die, and a second plurality of interconnects electrically coupling the second die to the substrate.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: January 8, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Eiichi Nakano
  • Patent number: 10141259
    Abstract: Semiconductor devices having one or more vias filled with a transparent and electrically conductive material are disclosed herein. In one embodiment, a semiconductor device includes a first semiconductor die stacked over a second semiconductor die. The first semiconductor die can include at least one via that is axially aligned with a corresponding via of the second semiconductor die. The vias of the first and second semiconductor dies can be filled with a transparent and electrically conductive material that both electrically and optically couples the first and second semiconductor dies.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: November 27, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Eiichi Nakano, Mark E. Tuttle
  • Patent number: 8183017
    Abstract: The ability and speed with which a coryneform bacterium can produce L-lysine are improved when the coryneform bacterium contains an aspartokinase in which feedback inhibition by L-lysine and L-threonine is substantially desensitized. This is accomplished by successively enhancing the DNA coding for dihydrodipicolinate reductase, the DNA coding for dihydrodipicolinate synthase, the DNA coding for diaminopimelate decarboxylase, and the DNA coding for diaminopimelate dehydrogenase.
    Type: Grant
    Filed: October 29, 2010
    Date of Patent: May 22, 2012
    Assignee: Ajinomoto Co., Inc.
    Inventors: Seiko Otsuna, Masakazu Sugimoto, Masako Izui, Atsushi Hayakawa, Eiichi Nakano, Masaki Kobayashi, Yasuhiko Yoshihara, Tsuyoshi Nakamatsu