Patents by Inventor Eiichi Sekine

Eiichi Sekine has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6417682
    Abstract: A calibration method for calibrating a semiconductor testing apparatus before mounting semiconductor devices for performing a testing of electric characteristics thereof, the testing apparatus having a driver which generates and outputs a signal, and a socket with a plurality of terminals for receiving pins and transferring signals therethrough. The calibration method includes mounting a test board having a plurality of pins onto the socket and connecting each of the pins of the test board with a respective terminal of the socket, transferring the signal of the driver to the terminals of the test board, detecting the signal of the driver that has reached the test board, and setting an output timing of the signal of the driver based on the signal detected.
    Type: Grant
    Filed: May 19, 1999
    Date of Patent: July 9, 2002
    Assignee: Advantest Corporation
    Inventors: Toshikazu Suzuki, Hiroyuki Nagai, Noriyoshi Kozuka, Yukio Ishigaki, Shigeru Matsumura, Takashi Sekizuka, Hiroyuki Shiotsuka, Hiroyuki Hama, Eiichi Sekine
  • Patent number: 5862088
    Abstract: In a memory testing apparatus wherein a plurality of function tests are continuously carried out for a semiconductor memory and a decision as to whether or not a failure relieving analysis of the memory should be performed is rendered upon completion of each function test, a failure cell counter 15 is provided at the rear stage of a failure analysis memory 13. When a failure memory cell is detected in a memory under test MUT in each function test, the number of failure cells of the memory under test is counted by the failure cell counter. A main controller controls operations of the memory testing apparatus ST such that a failure relieving analysis of the memory under test is performed only when the number of failure memory cells detected in the function test performed this time is greater than the number of failure memory cells detected in the preceding function test.
    Type: Grant
    Filed: April 14, 1998
    Date of Patent: January 19, 1999
    Assignee: Advantest Corporation
    Inventors: Hiroshi Takemoto, Eiichi Sekine
  • Patent number: 4878743
    Abstract: In an automotive mirror using an electrochromic element, the electrochromic element comprises a first electrode made of a transparent conductive layer laminated on a substantially rectangular glass substrate, two EC (electrochromic) layers disposed opposing each other with a solid electrolyte layer placed between them, a second electrode made of a reflective metal film and an insulative/protective layer disposed outside the second electrode. There are formed on the first electrode longitudinally and laterally in positions off the adjoining EC layer, strip-shaped metal films considerably superior in conductivity to the first electrode.
    Type: Grant
    Filed: June 7, 1988
    Date of Patent: November 7, 1989
    Assignee: Ichikoh Industries Limited
    Inventors: Toyoshi Aikawa, Eiichi Sekine