Patents by Inventor Eiji Hasegawa

Eiji Hasegawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20040003281
    Abstract: An information processing apparatus is connectable to a user device over a network. The apparatus includes a processor. The processor transmits, in response to reception of a request for a particular item of content, an identification of a security scheme which is applicable to transmission of the particular item of content in accordance with a license policy. When the item of content can be received by the user device in the security scheme, the processor transmits the item of content in the security scheme.
    Type: Application
    Filed: October 29, 2002
    Publication date: January 1, 2004
    Applicant: FUJITSU LIMITED
    Inventors: Toshihiro Sonoda, Eiji Hasegawa, Kouichi Yasaki
  • Patent number: 6586293
    Abstract: To prevent a thick gate oxide film from being damaged by a cleaning and hydrofluoric-acid treatment preprocess performed prior to formation of a thin gate oxide film. A thick first gate oxide film is formed, and an insulating film, having etching resistance against the cleaning and hydrofluoric-acid treatment process for formation of thin second gate oxide film, is formed in an upper region of the first gate oxide film. A resist is then formed in a region where a thick gate insulating film is to be formed, and etching is performed on the first gate oxide film with the resist as a mask. The resist is stripped, then cleaning and hydrofluoric-acid treatment are performed on the silicon surface in a region where a thin gate insulating film is to be formed, and the thin second gate oxide film is formed.
    Type: Grant
    Filed: January 17, 2001
    Date of Patent: July 1, 2003
    Assignee: NEC Corporation
    Inventor: Eiji Hasegawa
  • Patent number: 6555483
    Abstract: A gate insulation film includes nitrogen, oxygen and silicon as constituent elements thereof. The nitrogen concentration profile of the gate insulation film in the thickness direction has a maximum concentration in the vicinity of the top surface of the gate insulation film and substantially zero concentration in the vicinity of the silicon substrate. The specified nitrogen profile is obtained by a steep rising slope and a relatively steep falling slope of the temperature profile with time in the step of nitriding a silicon oxide film to form a silicon oxynitride film.
    Type: Grant
    Filed: November 6, 2001
    Date of Patent: April 29, 2003
    Assignee: NEC Corporation
    Inventor: Eiji Hasegawa
  • Patent number: 6530046
    Abstract: There are provided a semiconductor device and a function module test method, capable of reducing the test time of function modules and reducing the number of test pins. This semiconductor device is formed so as to make test inputs and test outputs of a plurality of function modules having the same function respectively common, conduct tests on arbitrarily selected function modules simultaneously in parallel, and give a pass/fail decision on the semiconductor device including the function modules on the basis of results of comparison between a test result of arbitrary one function module and test results of other function modules.
    Type: Grant
    Filed: February 23, 2000
    Date of Patent: March 4, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Eiji Hasegawa, Yoshikatu Hatagaki, Ayumi Ishii, Hidekazu Saito, Masaki Kume
  • Publication number: 20030018979
    Abstract: A method of providing means for smooth communication between audiences in a television and a TV communication terminal used for the method are provided. An address of a communication server is transmitted via a television or a communication network to the TV communication terminal that can receive the television and make a connection with the communication network. A plurality of communication channels is prepared for one television program. An attribution of the audience using the TV communication terminal and attributions of the communication channels are compared, so that the audience receiving the television program can use an optimal communication channel for communicating with other audiences.
    Type: Application
    Filed: October 30, 2001
    Publication date: January 23, 2003
    Applicant: FUJITSU LIMITED
    Inventors: Eiji Hasegawa, Toru Kamiwada, Toshihiro Azami
  • Patent number: 6445033
    Abstract: A gate-insulating film of the present invention is a gate-insulating film having a polycrystalline film made of a metal oxide, in which a grain boundary plane extending in parallel with the polycrystalline film is present at the position of a predetermined thickness of the polycrystalline film and grain boundaries extending in the film-thickness direction of polycrystals configuring the polycrystalline film are discontinuous at the grain boundary plane.
    Type: Grant
    Filed: June 30, 2000
    Date of Patent: September 3, 2002
    Assignee: NEC Corporation
    Inventor: Eiji Hasegawa
  • Publication number: 20020076869
    Abstract: A gate insulation film includes nitrogen, oxygen and silicon as constituent elements thereof. The nitrogen concentration profile of the gate insulation film in the thickness direction has a maximum concentration in the vicinity of the top surface of the gate insulation film and substantially zero concentration in the vicinity of the silicon substrate. The specified nitrogen profile is obtained by a steep rising slope and a relatively steep falling slope of the temperature profile with time in the step of nitriding a silicon oxide film to form a silicon oxynitride film.
    Type: Application
    Filed: November 6, 2001
    Publication date: June 20, 2002
    Applicant: NEC Corporation
    Inventor: Eiji Hasegawa
  • Publication number: 20020055273
    Abstract: In a semiconductor device including a semiconductor substrate and a gate electrode layer, a single silicon oxide nitride (SiON) layer is sandwiched by the semiconductor substrate and the gate electrode layer.
    Type: Application
    Filed: November 7, 2001
    Publication date: May 9, 2002
    Applicant: NEC Corporation
    Inventor: Eiji Hasegawa
  • Publication number: 20010052618
    Abstract: A semiconductor device is fabricated by injecting fluorine into a region of a semiconductor substrate other than a region of the semiconductor substrate where a thinnest gate insulating film is to be formed, among a plurality of regions where gate insulating films are to be formed. Then, the semiconductor substrate with fluorine injected therein is oxidized to form an oxide film in the plurality of regions. A surface of the oxide film is nitrided to turn a surface layer thereof into an oxynitride film or form a nitride film on the surface of the oxide film. The semiconductor device has a plurality of gate insulating films of different thicknesses which contain nitrogen in their surface layers.
    Type: Application
    Filed: June 19, 2001
    Publication date: December 20, 2001
    Applicant: NEC Corporation
    Inventor: Eiji Hasegawa
  • Patent number: 6091109
    Abstract: The present invention provides a structure comprising: a first oxide film having a first thickness and extending on a first region of a semiconductor substrate; and a second oxide film having a second thickness which is thicker than the first thickness of the first oxide film, the second oxide film extending on a second region of the semiconductor substrate, wherein the first oxide film contains a first substance which is capable of decreasing an oxidation rate of a thermal oxidation process, while the second oxide film contains a second substance which is capable of increasing the oxidation rate of the thermal oxidation process.
    Type: Grant
    Filed: May 11, 1999
    Date of Patent: July 18, 2000
    Assignee: NEC Corporation
    Inventor: Eiji Hasegawa
  • Patent number: 6037651
    Abstract: A semiconductor device with a multi-level insulator formed on a semiconductor substrate is provided, which enables to restraint of impurity atoms doped into a material contacted with the insulator from diffusing into the insulator. The multi-level structured insulator contains a first dielectric film formed on the substrate and a second dielectric film formed on the first dielectric film. The first dielectric film is thicker than the second dielectric film so that an interface of the first and second dielectric films exists at a level higher than the central level of the insulator. The first dielectric film is made of an oxide of a semiconductor constituting the substrate. The second dielectric film is made of a nitride or oxynitride of the semiconductor constituting the substrate. The insulator preferably contains only the first and second dielectric films to have a two-level structure.
    Type: Grant
    Filed: May 10, 1996
    Date of Patent: March 14, 2000
    Assignee: NEC Corporation
    Inventor: Eiji Hasegawa
  • Patent number: 5986780
    Abstract: This specification discloses a hologram reconstructing apparatus having interference fringe forming means for forming optical interference fringes in conformity with an input signal, information input means for successively inputting different bits of interference fringe information to the interference fringe forming means, and illuminating means for illuminating the interference fringe forming means with a plurality of beams of light differing in wavefront from one another.
    Type: Grant
    Filed: February 10, 1997
    Date of Patent: November 16, 1999
    Assignee: Canon Kabushiki Kaisha
    Inventors: Toshiyuki Sudo, Eiji Hasegawa
  • Patent number: 5972800
    Abstract: A method for fabricating a semiconductor device with a multi-level insulator formed on a semiconductor substrate is provided, which enables restraint of impurity atoms doped into a material contacted with the insulator from diffusing into the insulator and substrate. A first dielectric film formed on the substrate is made of an oxide of a semiconductor constituting the substrate by thermal treatment of the substrate in an oxygen atmosphere. The second dielectric film is disposed at the interface of the substrate and first dielectric and is made of a nitride or oxynitride of the semiconductor constituting the substrate by thermal treatment of the substrate and first dielectric in a nitride atmosphere. The insulator preferably contains only the first and second dielectric films to have a two-level structure. The insulator may further contain a third dielectric film formed over the multi-level structure, thereby having a three-level insulator structure.
    Type: Grant
    Filed: July 9, 1997
    Date of Patent: October 26, 1999
    Assignee: NEC Corporation
    Inventor: Eiji Hasegawa
  • Patent number: 5460992
    Abstract: A non-volatile memory device with a multi-layered gate electrode structure is fabricated by forming a floating gate electrode and a thermally oxidized silicon film on surfaces inclusive of a surface of the multi-layered gate electrode structure having a control gate electrode, and then forming, by a thermal nitrifying treatment, a thermally nitrified oxidized silicon film at an interface between the thermally oxidized silicon film and the multi-layered gate electrode structure. Diffusion of impurity into a multi-layered gate electrode structure of the memory is prevented and also leakage current due to mismatching at the film interface is reduced.
    Type: Grant
    Filed: May 11, 1995
    Date of Patent: October 24, 1995
    Assignee: NEC Corporation
    Inventor: Eiji Hasegawa