Abstract: A test circuit and a method of monitoring a manufacturing process of a semiconductor integrated circuit using the test circuit are provided. The test circuit comprises elements to be tested; a selection circuit for sequentially selecting at least one of the elements at a time. The test circuit and pads used for testing the elements are placed within a scribe line on a semiconductor wafer.

Abstract: A test circuit and a method of monitoring a manufacturing process of a semiconductor integrated circuit using the test circuit are provided. The test circuit comprises elements to be tested; a selection circuit for sequentially selecting at least one of the elements at a time. The test circuit and pads used for testing the elements are placed within a scribe line on a semiconductor wafer.

Abstract: A test circuit and a method of monitoring a manufacturing process of a semiconductor integrated circuit using the test circuit are provided. The test circuit comprises elements to be tested; a selection circuit for sequentially selecting at least one of the elements at a time. The test circuit and pads used for testing the elements are placed within a scribe line on a semiconductor wafer.

Abstract: A test circuit and a method of monitoring a manufacturing process of a semiconductor integrated circuit using the test circuit are provided. The test circuit comprises elements to be tested; a selection circuit for sequentially selecting at least one of the elements at a time. The test circuit and pads used for testing the elements are placed within a scribe line on a semiconductor wafer.

Abstract: A basic cell is disclosed, which is small in area and has sufficient connection flexibility. for achieving a semiconductor integrated circuit with a higher density and a reduced manufacturing cost. In a basic cell, a terminal wire, which is connected to a transistor terminal with a contact, is placed in a first metal wiring layer, and a plurality of terminal wire connection points, which can be connected to a second metal wire through a first via, are provided on the terminal wire. Further, in a semiconductor integrated circuit, a circuit wire in a second metal wiring layer is placed along grid points with a fixed pitch, and is connected to a terminal connection point of a transistor terminal, which is displaced from the grid points, through a terminal wire provided in the first metal wiring layer.

Abstract: A test circuit and a method of monitoring a manufacturing process of a semiconductor integrated circuit using the test circuit are provided. The test circuit comprises elements to be tested: a selection circuit for sequentially selecting at least one of the elements at a time. The test circuit and pads used for testing the elements are placed within a scribe line on a semiconductor wafer.

Abstract: The gate width of a field effect transistor is increased to a value greater than a size of an active region by forming an inclined portion of a gate electrode. As a result, the current driving capability of a field effect transistor is increased without degrading the integration density. The driving capability of the transistor can be further effectively increased by forming an expanded portion of the active region at a location corresponding to the inclined portion of the gate electrode thereby reducing the resistance of the diffusion layer.

Abstract: After forming a low concentration impurity layer by ion implanting an impurity into a semiconductor substrate 1 by using a gate electrode 7 on the semiconductor substrate 1 as a mask, side walls composed of films having a large etching resistivity with respect to an interlayer dielectric film 13 are formed on side surfaces of the gate electrode 7 and a gate oxide film 6 located beneath the gate electrode 7. Subsequently, the interlayer dielectric film 13 is formed over the whole surface, and a contact hole 18 having a part of side walls constituted by the first-mentioned side walls 8 and a field oxide film 2 is formed. A high concentration impurity layer is formed by implanting an impurity through the contact hole 18.

Abstract: A method of gas reaction process control in which plasma gas generated in a location different than a location at which a specimen is held is transported to a location at which the specimen is held and gas processing of the specimen is carried out. A control electrode with porous structure permeable to the plasma gas is provided in the transportation route and a voltage is applied to the control electrode voltage for adjusting the specimen surface potential so as to prevent degradation of the specimen due to specimen surface potential.