Patents by Inventor Ellie Y. Yieh

Ellie Y. Yieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240120195
    Abstract: A method includes forming a conductive material on a first dielectric layer, exposing the conductive material to aniline to produce a passivated surface of the conductive material, and after exposing the conductive material to aniline, forming a second dielectric layer on the first dielectric layer using a deposition process. The deposition process is a water-free and plasma-free deposition process, and the second dielectric layer does not form on the passivated surface of the conductive material.
    Type: Application
    Filed: October 6, 2022
    Publication date: April 11, 2024
    Inventors: Keith T. Wong, Srinivas D. Nemani, Ellie Y. Yieh, Andrew C. Kummel, Yunil Cho, James Huang
  • Publication number: 20240085810
    Abstract: A method and apparatus for performing post-exposure bake operations is described herein. After exposure of photoresist on a substrate, the substrate is heated during a baking process to facilitate protection of the resist. The baking process is performed in a vacuum environment at sub-atmospheric pressures. After baking at reduced pressure, the substrate is cooled. The cooling process is performed at sub-atmospheric pressures. Further development of the resist is performed at ambient pressures.
    Type: Application
    Filed: September 7, 2023
    Publication date: March 14, 2024
    Inventors: Huixiong DAI, Mangesh Ashok BANGAR, Chih-An HSU, Srinivas D. NEMANI, Dmitry LUBOMIRSKY, Ellie Y. YIEH
  • Patent number: 11914299
    Abstract: A method for enhancing the depth of focus process window during a lithography process includes applying a photoresist layer comprising a photoacid generator on a material layer disposed on a substrate, exposing a first portion of the photoresist layer unprotected by a photomask to light radiation in a lithographic exposure process, providing a thermal energy to the photoresist layer in a post-exposure baking process, applying an electric field or a magnetic field while performing the post-exposure baking process, and dynamically changing a frequency of the electric field as generated while providing the thermal energy to the photoresist layer.
    Type: Grant
    Filed: August 29, 2022
    Date of Patent: February 27, 2024
    Assignee: Applied Materials, Inc.
    Inventors: Huixiong Dai, Mangesh Ashok Bangar, Srinivas D. Nemani, Christopher S. Ngai, Ellie Y. Yieh
  • Publication number: 20240038527
    Abstract: A method includes depositing a flowable film on a substrate by providing a first input flow, the first input flow including plasma effluents of a first precursor, removing a portion of the flowable film from a sidewall of a feature defined within the substrate to obtain a remaining portion of the flowable film by providing a second input flow, the second input flow including plasma effluents of a second precursor, reducing hydrogen content of the remaining portion of the flowable film to obtain a densified film by providing a third input flow, the third input flow including plasma effluents of a third precursor, and treating the densified film in accordance with a film treatment process.
    Type: Application
    Filed: July 26, 2022
    Publication date: February 1, 2024
    Inventors: Bhargav S. Citla, Srinivas D. Nemani, Purvam Modi, Ellie Y. Yieh
  • Patent number: 11880137
    Abstract: Methods and apparatuses for minimizing line edge/width roughness in lines formed by photolithography are provided. In one example, a method of processing a substrate includes applying a photoresist layer comprising a photoacid generator to on a multi-layer disposed on a substrate, wherein the multi-layer comprises an underlayer formed from an organic material, inorganic material, or a mixture of organic and inorganic materials, exposing a first portion of the photoresist layer unprotected by a photomask to a radiation light in a lithographic exposure process, and applying an electric field or a magnetic field to alter movement of photoacid generated from the photoacid generator substantially in a vertical direction.
    Type: Grant
    Filed: March 23, 2023
    Date of Patent: January 23, 2024
    Assignee: Applied Materials, Inc.
    Inventors: Huixiong Dai, Mangesh Ashok Bangar, Srinivas D. Nemani, Ellie Y. Yieh, Steven Hiloong Welch, Christopher S. Ngai
  • Patent number: 11881411
    Abstract: The present disclosure provides methods for performing an annealing process on a metal containing layer in TFT display applications, semiconductor or memory applications. In one example, a method of forming a metal containing layer on a substrate includes supplying an oxygen containing gas mixture on a substrate in a processing chamber, the substrate comprising a metal containing layer disposed on an optically transparent substrate, maintaining the oxygen containing gas mixture in the processing chamber at a process pressure between about 2 bar and about 50 bar, and thermally annealing the metal containing layer in the presence of the oxygen containing gas mixture.
    Type: Grant
    Filed: May 4, 2021
    Date of Patent: January 23, 2024
    Assignee: Applied Materials, Inc.
    Inventors: Kaushal K. Singh, Mei-Yee Shek, Srinivas D. Nemani, Ellie Y. Yieh
  • Patent number: 11862458
    Abstract: Exemplary processing methods may include forming a plasma of a silicon-containing precursor. The methods may include depositing a flowable film on a semiconductor substrate with plasma effluents of the silicon-containing precursor. The processing region may be at least partially defined between a faceplate and a substrate support on which the semiconductor substrate is seated. A bias power may be applied to the substrate support from a bias power source. The methods may include forming a plasma of a hydrogen-containing precursor within the processing region of the semiconductor processing chamber. The methods may include etching the flowable film from a sidewall of the feature within the semiconductor substrate with plasma effluents of the hydrogen-containing precursor. The methods may include densifying remaining flowable film within the feature defined within the semiconductor substrate with plasma effluents of the hydrogen-containing precursor.
    Type: Grant
    Filed: September 8, 2021
    Date of Patent: January 2, 2024
    Assignee: Applied Materials, Inc.
    Inventors: Bhargav S. Citla, Soham Asrani, Joshua Rubnitz, Srinivas D. Nemani, Ellie Y. Yieh
  • Publication number: 20230386829
    Abstract: Embodiments of the disclosure relate to methods for forming silicon based gapfill within substrate features. A flowable silicon film is formed within the feature with a greater thickness on the bottom and top surfaces than the sidewall surface. An etch plasma removes the silicon film from the sidewall surface. A conversion plasma is used to convert the silicon film to a silicon based gapfill (e.g., silicon oxide). In some embodiments, the silicon film is preferentially converted on the top and bottom surface before being etched from the sidewall surface.
    Type: Application
    Filed: May 27, 2022
    Publication date: November 30, 2023
    Applicant: Applied Materials, Inc.
    Inventors: Soham Asrani, Bhargav S. Citla, Srinivas D. Nemani, Ellie Y. Yieh
  • Publication number: 20230377875
    Abstract: Exemplary processing methods may include forming a plasma of a silicon-containing precursor. The methods may include depositing a flowable film on a semiconductor substrate with plasma effluents of the silicon-containing precursor. The processing region may be at least partially defined between a faceplate and a substrate support on which the semiconductor substrate is seated. A bias power may be applied to the substrate support from a bias power source. The methods may include forming a plasma of a hydrogen-containing precursor within the processing region of the semiconductor processing chamber. The methods may include etching the flowable film from a sidewall of the feature within the semiconductor substrate with plasma effluents of the hydrogen-containing precursor. The methods may include densifying remaining flowable film within the feature defined within the semiconductor substrate with plasma effluents of the hydrogen-containing precursor.
    Type: Application
    Filed: August 2, 2023
    Publication date: November 23, 2023
    Applicant: Applied Materials, Inc.
    Inventors: Bhargav S. Citla, Soham Asrani, Joshua Rubnitz, Srinivas D. Nemani, Ellie Y. Yieh
  • Publication number: 20230377958
    Abstract: Methods for forming a transition metal material on a substrate and thermal processing such metal containing material in a cluster processing system are provided. In one embodiment, a method for a device structure for semiconductor devices includes forming a two-dimensional transition metal dichalcogenide layer on a substrate in a first processing chamber disposed in a cluster processing system, thermally treating the two-dimensional transition metal dichalcogenide layer to form a treated metal layer in a second processing chamber disposed in the cluster processing system, and forming a capping layer on the treated metal layer in a third processing chamber disposed in the cluster processing system.
    Type: Application
    Filed: July 31, 2023
    Publication date: November 23, 2023
    Inventors: Keith Tatseun WONG, Srinivas D. NEMANI, Ellie Y. YIEH
  • Patent number: 11798606
    Abstract: One or more embodiments described herein generally relate to patterning semiconductor film stacks. Unlike in conventional embodiments, the film stacks herein are patterned without the need of etching the magnetic tunnel junction (MTJ) stack. Instead, the film stack is etched before the MTJ stack is deposited such that the spin on carbon layer and the anti-reflective coating layer are completely removed and a trench is formed within the dielectric capping layer and the oxide layer. Thereafter, MTJ stacks are deposited on the buffer layer and on the dielectric capping layer. An oxide capping layer is deposited such that it covers the MTJ stacks. An oxide fill layer is deposited over the oxide capping layer and the film stack is polished by chemical mechanical polishing (CMP). The embodiments described herein advantageously result in no damage to the MTJ stacks since etching is not required.
    Type: Grant
    Filed: May 24, 2021
    Date of Patent: October 24, 2023
    Assignee: APPLIED MATERIALS, INC.
    Inventors: John O. Dukovic, Srinivas D. Nemani, Ellie Y. Yieh, Praburam Gopalraja, Steven Hiloong Welch, Bhargav S. Citla
  • Publication number: 20230326925
    Abstract: Embodiments of the disclosure advantageously provide semiconductor devices CFET in particular and methods of manufacturing such devices having a fully strained superlattice structure with channel layers that are substantially free of defects and release layers having a reduced selective removal rate. The CFET described herein comprise a vertically stacked superlattice structure on a substrate, the vertically stacked superlattice structure comprising: a first hGAA structure on the substrate; a sacrificial layer on a top surface of the first hGAA structure, the sacrificial layer comprising silicon germanium (SiGe) having a germanium content in a range of from greater than 0% to 50% on an atomic basis; and a second hGAA structure on a top surface of the sacrificial layer. Each of the first hGAA and the second hGAA comprise alternating layers of nanosheet channel layer that comprise silicon (Si) and nanosheet release layer that comprise doped silicon germanium (SiGe).
    Type: Application
    Filed: April 7, 2022
    Publication date: October 12, 2023
    Applicant: Applied Materials, Inc.
    Inventors: Andrew Anthony Cockburn, Vanessa Pena, Daniel Philippe Cellier, John Tolle, Thomas Kirschenheiter, Wei Hong, Ellie Y. Yieh, Mehul Naik, Seshadri Ramaswami
  • Publication number: 20230298893
    Abstract: An annealing system is provided that includes a chamber body that defines a chamber, a support to hold a workpiece and a robot to insert the workpiece into the chamber. The annealing system also includes a first gas supply to provide a hydrogen gas, a pressure source coupled to the chamber to raise a pressure in the chamber to at least 5 atmospheres, and a controller configured to cause the robot to transport a workpiece having a metal film thereon into the chamber, where the metal film contains fluorine on a surface or embedded within the metal film, to cause the first gas supply to supply the hydrogen gas to the chamber and form atomic hydrogen therein, and to cause the pressure source to raise a pressure in the chamber to at least 5 atmospheres while the workpiece is held on the support in the chamber.
    Type: Application
    Filed: May 26, 2023
    Publication date: September 21, 2023
    Inventors: Keith Tatseun WONG, Thomas Jongwan KWON, Sean KANG, Ellie Y. YIEH
  • Patent number: 11764058
    Abstract: Methods of reducing wafer bowing in 3D DRAM devices are described using a 3-color process. A plurality of film stacks are formed on a substrate surface, each of the film stacks comprises two doped SiGe layers having different dopant amounts and/or Si:Ge ratios and a doped silicon layer. 3D DRAM devices are also described.
    Type: Grant
    Filed: September 28, 2021
    Date of Patent: September 19, 2023
    Assignee: Applied Materials, Inc.
    Inventors: Arvind Kumar, Mahendra Pakala, Ellie Y. Yieh, John Tolle, Thomas Kirschenheiter, Anchuan Wang, Zihui Li
  • Patent number: 11756803
    Abstract: A high-pressure processing system for processing a layer on a substrate includes a first chamber, a support to hold the substrate in the first chamber, a second chamber adjacent the first chamber, a foreline to remove gas from the second chamber, a vacuum processing system configured to lower a pressure within the second chamber to near vacuum, a valve assembly between the first chamber and the second chamber to isolate the pressure within the first chamber from the pressure within the second chamber, a gas delivery system configured to increase the pressure within the first chamber to at least 10 atmospheres while the first chamber is isolated from the second chamber, an exhaust system comprising an exhaust line to remove gas from the first chamber, and a common housing surrounding both the first gas delivery module and the second gas delivery module.
    Type: Grant
    Filed: November 29, 2022
    Date of Patent: September 12, 2023
    Assignee: Applied Materials, Inc.
    Inventors: Qiwei Liang, Srinivas D. Nemani, Sean S. Kang, Adib Khan, Ellie Y. Yieh
  • Patent number: 11756828
    Abstract: Methods for forming a transition metal material on a substrate and thermal processing such metal containing material in a cluster processing system are provided. In one embodiment, a method for a device structure for semiconductor devices includes forming a two-dimensional transition metal dichalcogenide layer on a substrate in a first processing chamber disposed in a cluster processing system, thermally treating the two-dimensional transition metal dichalcogenide layer to form a treated metal layer in a second processing chamber disposed in the cluster processing system, and forming a capping layer on the treated metal layer in a third processing chamber disposed in the cluster processing system.
    Type: Grant
    Filed: November 20, 2018
    Date of Patent: September 12, 2023
    Assignee: Applied Materials, Inc.
    Inventors: Keith Tatseun Wong, Srinivas D. Nemani, Ellie Y. Yieh
  • Publication number: 20230229089
    Abstract: Methods and apparatuses for minimizing line edge/width roughness in lines formed by photolithography are provided. In one example, a method of processing a substrate includes applying a photoresist layer comprising a photoacid generator to on a multi-layer disposed on a substrate, wherein the multi-layer comprises an underlayer formed from an organic material, inorganic material, or a mixture of organic and inorganic materials, exposing a first portion of the photoresist layer unprotected by a photomask to a radiation light in a lithographic exposure process, and applying an electric field or a magnetic field to alter movement of photoacid generated from the photoacid generator substantially in a vertical direction.
    Type: Application
    Filed: March 23, 2023
    Publication date: July 20, 2023
    Applicant: Applied Materials, Inc.
    Inventors: Huixiong DAI, Mangesh Ashok BANGAR, Srinivas D. NEMANI, Ellie Y. YIEH, Steven Hiloong WELCH, Christopher S. NGAI
  • Patent number: 11705337
    Abstract: An annealing system is provided that includes a chamber body that defines a chamber, a support to hold a workpiece and a robot to insert the workpiece into the chamber. The annealing system also includes a first gas supply to provide a hydrogen gas, a pressure source coupled to the chamber to raise a pressure in the chamber to at least 5 atmospheres, and a controller configured to cause the robot to transport a workpiece having a metal film thereon into the chamber, where the metal film contains fluorine on a surface or embedded within the metal film, to cause the first gas supply to supply the hydrogen gas to the chamber and form atomic hydrogen therein, and to cause the pressure source to raise a pressure in the chamber to at least 5 atmospheres while the workpiece is held on the support in the chamber.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: July 18, 2023
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Keith Tatseun Wong, Thomas Jongwan Kwon, Sean Kang, Ellie Y. Yieh
  • Patent number: 11682556
    Abstract: A method of forming graphene layers is disclosed. A method of improving graphene deposition is also disclosed. Some methods are advantageously performed at lower temperatures. Some methods advantageously provide graphene layers with lower resistance. Some methods advantageously provide graphene layers in a relatively short period of time.
    Type: Grant
    Filed: February 15, 2022
    Date of Patent: June 20, 2023
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Jie Zhou, Erica Chen, Qiwei Liang, Chentsau Chris Ying, Srinivas D. Nemani, Ellie Y. Yieh
  • Publication number: 20230161260
    Abstract: A method and apparatus for performing post-exposure bake cooling operations is described herein. The method begins by post exposure baking a substrate disposed on heated substrate support in a process chamber, the process chamber having a showerhead. The heated substrate support is moved to increase a distance between the heated substrate support and a cooled plate of the showerhead. The substrate is separated from the heated substrate support using a substrate lifting device. The substrate is moved into a close proximity to the cooled showerhead. The substrate is cooled until the substrate is less than about 70 degrees Celsius. The substrate is spaced away from the cooled showerhead using the substrate lifting device and aligning the substrate with a substrate transfer passage of the processing chamber for removal by a robot.
    Type: Application
    Filed: October 5, 2022
    Publication date: May 25, 2023
    Inventors: Dmitry LUBOMIRSKY, Douglas A. BUCHBERGER, Jr., Hyunjun KIM, Alan L. TSO, Shekhar ATHANI, Qiwei LIANG, Ellie Y. YIEH