Patents by Inventor Elliot D. Garbus

Elliot D. Garbus has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6088421
    Abstract: A method and apparatus for monitoring an event is disclosed. In one embodiment, a ratio counter is provided which includes a first counter having a first count and a second counter having a second count. The method increments the first count of the first counter on an occurrence of an event by a first device and shifts the ratio counter to the right by a predetermined number of bits when the first count reaches a maximum count. The method further takes a ratio between the first count and the second count where the ratio indicates the relative occurrence of the event by the first device and a second device. In another embodiment, the method decrements the second count of the second counter when the first count reaches a maximum count. In yet another embodiment, the method decrements the first count of the first counter and the second count of the second counter when the first count reaches a maximum count.
    Type: Grant
    Filed: July 28, 1998
    Date of Patent: July 11, 2000
    Assignee: Intel Corporation
    Inventors: Ravi S. Rao, Elliot D. Garbus
  • Patent number: 5657475
    Abstract: The system and method described provide for the detection and protection of memory accesses without the overhead typically incurred by memory management units. The processor includes a guarded memory unit, which monitors memory accesses to be performed by monitoring transmissions across the memory bus. The guarded memory unit includes a plurality of registers which identify memory addresses and modes which can cause a memory protection or detection violation to occur. If a memory protection violation occurs, a cancel signal is issued to cancel the memory operation prior to completion in order to protect the memory from unauthorized accesses. If a memory violation is detected, the memory operation is permitted to complete and a fault signal is issued to the processor to identify that a memory violation has been detected.
    Type: Grant
    Filed: January 4, 1996
    Date of Patent: August 12, 1997
    Assignee: Intel Corporation
    Inventors: Byron R. Gillespie, Elliot D. Garbus, Mitchell A. Kahn, Thomas M. Johnson, Dennis M. O'Connor, Jay S. Heeb
  • Patent number: 5513337
    Abstract: The system and method described provide for the detection and protection of memory accesses without the overhead typically incurred by memory management units. The processor includes a guarded memory unit, which monitors memory accesses to be performed by monitoring transmissions across the memory bus. The guarded memory unit includes a plurality of registers which identify memory addresses and modes which can cause a memory protection or detection violation to occur. If a memory protection violation occurs, a cancel signal is issued to cancel the memory operation prior to completion in order to protect the memory from unauthorized accesses. If a memory violation is detected, the memory operation is permitted to complete and a fault signal is issued to the processor to identify that a memory violation has been detected.
    Type: Grant
    Filed: May 25, 1994
    Date of Patent: April 30, 1996
    Assignee: Intel Corporation
    Inventors: Byron R. Gillespie, Elliot D. Garbus, Mitchell A. Kahn, Thomas M. Johnson, Dennis M. O'Connor, Jay S. Heeb